In what may be a defining moment for electronic system level (ESL) design, TSMC this June announced Reference Flow 11.0, which extends TSMC's Open Innovation Platform to system-level design. Why was the flow developed, what was Cadence's role, and what was learned in the development of this flow? To get some answers, I recently spoke to Ashok Mehta, senior manager for design and technology platforms at TSMC, and Leonard Drucker, solution architect at Cadence.
Why an ESL Reference Flow?
The first question you might have is why the world's largest foundry, which so far has focused on IC implementation flows, would move upstream to ESL. According to Ashok, TSMC noticed that there are fewer and fewer semiconductor startups as process nodes shrink and design costs escalate. Something needed to be done about the front end, but what? RTL alone was not enough, TSMC decided, given the potential productivity gains and the lack of validated flows at the electronic system level.
Unlike rules-based, back-end flows, TSMC can't guarantee any particular result if the ESL reference flow is followed. The point, Ashok said, is to "show one good, proven way to do things. This is a proven way to use a methodology that is very new to most people. They can look at it and change it to their liking. We think it will give them a head start."
What's in the flow? Ashok identified four components:
- Virtual platform modeling
- Power, performance and area models
- ESL verification
- High-level synthesis
Cadence worked with TSMC on ESL verification and high-level synthesis. Since Ashok and Leonard were primarily involved in verification, that's where the rest of this blog posting focuses.
Refine and Reuse
ESL has been around for many years, Ashok noted, but a critical piece has been missing. Algorithmic models and testbenches are typically not reused in virtual platforms, and virtual platform transaction-level models (TLMs) generally can't be brought into "hybrid" simulations with RTL blocks. "I should be able to reuse my models and testbenches verbatim, take the whole thing, and use it to drive the next stage," Ashok said. "In Reference Flow 11.0 this is doable."
Ashok identified four components of a "refine and reuse" verification flow: constraint-driven verification planning, testbench refinement and reuse, design refinement and reuse, and unified debug. All are represented in Reference Flow 11.0, and this is where Cadence's verification technology, which allows reuse across multiple abstraction levels, came into the picture.
"TSMC supplied the framework, the ideas, and the direction we needed to go, and we filled in the details," Leonard said. Cadence contributions included the definition of different abstraction levels, a methodology for using models across abstraction levels, and a means to physically connect OVM testbenches to TLM 2.0 models. Tools used in the refine and reuse verification flow include Incisive Enterprise Simulator, Incisive Enterprise Manager, and Incisive Enterprise Planner. (Additionally, C-to-Silicon Compiler is used for Reference Flow 11.0 high-level synthesis).
Challenges and Lessons Learned
Ashok thought building an ESL reference flow would be fairly easy, especially since Reference Flow 11.0 is a block-level flow. He came to this realization: "Whatever looks simple, is not." Instead of a month or two, it took up to six months to develop and implement the flow. The good news is that customers don't have to replicate that effort.
One of the challenges was learning how to include purely algorithmic models, a so-called "stage 0," into the refine and reuse flow. Ashok said: "We had very challenging discussions on adding an algorithm stage, where you can show how to verify something using a C++ testbench and a live data stream." Leonard said: "We learned the importance of taking into account the pure functional environment, the stage 0. TSMC's ideas helped broaden our methodology to make sure we took that initial step into account."
"Another lesson learned is that the verification team can really play a key role in the adoption and deployment of ESL," Leonard said. "The verification team is always reaching up to higher levels of abstraction."
There will be more lessons learned as TSMC moves to its next reference flow, which will use an SoC-level example. Meanwhile, it appears to me that Reference Flow 11.0 represents collaboration in its deepest sense, and that it will do much to drive marketplace acceptance and adoption of ESL.
System Realization webinars Oct. 6 and Nov. 3 will provide more information about the TSMC Reference Flow 11.0. Click here for details.