You probably know that silicon-on-insulator (SOI) technology
offers lower power and/or better performance than bulk CMOS, and that qualified
IP libraries are available. But what's the impact on the digital design flow?
Fairly minimal, but there are a few things you need to know about timing and
signal-integrity analysis, according to an August 25 webinar presentation by
ARM and Cadence.
Entitled "Are You Ready for Silicon On Insulator Design
Process," the webinar was presented by Mike Jacobs,
senior product manager at Cadence, and Remy Pottier, head of SOI marketing and
business development at ARM. The webinar was the second in a series of Digital
Implementation and Signoff webinars that will be rolling out over the next
few weeks. I blogged
separately about the first webinar, which covered on-chip variation and
statistical timing analysis.
As Remy noted, ARM has IBM 45nm SOI physical IP libraries
available today, and expects to roll out a 32nm library in the fourth quarter.
He also pointed to the wide variety of third-party IP currently available at
the Chipestimate.com SOI Portal.
He believes that SOI is ideal for gaming, networking, and base station markets,
and is increasingly attractive for mobile phone applications.
Modeling the History
What concerns digital designers the most (aside from wafer cost)
is the SOI "history effect," which occurs because the transistor body voltage
is dependent on previous switching activity. The same device will switch
differently depending on how active it was previously, because body voltage
builds up as activity increases and discharges as activity decreases. If it is
properly characterized in the physical IP library, the history effect is mostly
taken care of "under the hood" by the design tools - but there are a few
changes with respect to signoff timing analysis and signal-integrity analysis.
Timing analysis for SOI uses two libraries per
process-voltage-temperature (PVT) corner, compared to one library in bulk CMOS.
A Max-SOI library is characterized for the slowest possible operation, and a
Min-SOI library is characterized for the fastest possible operation. Once set
up, the timing tool will use Max-SOI for slower delays and Min-SOI for faster
delays. To check worst-case conditions, setup checks will use the Max-SOI
library on the launch edge and hold checks will use the Min-SOI library on the
Signal integrity is a little more complex. Traditional
signal-integrity analysis doesn't model the history effect correctly, Mike
noted; to do so accurately would require a transistor-level simulation. There
are several options:
design margins to account for history effect
- Use Min-SOI and Max-SOI noise
analysis views. This is more accurate, but still requires some
SPICE simulation on your critical paths.
None are perfect choices. To provide a better option, the Encounter Timing System offers a
"hybrid" noise analysis that uses Min-SOI and Max-SOI models, and only drops
down to transistor-level simulation for extremely noisy nets. In any case, Mike
said, SOI will not increase noise analysis runtime by more than 10 percent.
The Bottom Line
Any decision about whether to use SOI for a given
application depends on several key factors - performance, power, die size, and
cost. Concerns about design flows or physical IP should not be high on the
list, and that's why ARM and Cadence have an ongoing collaboration in support
of SOI chip development.
The Digital Implementation and Signoff webinars will be
roughly one week after each live presentation.