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MemCon Question #1: Are Memory Boom-and-Bust Cycles Inevitable?

Comments(0)Filed under: Industry Insights, 3D, memories, memory, DRAM, NAND, MemCon

Semiconductor memories are part of a commoditized, cost-per-bit driven market that's subject to repeated and predictable boom-and-bust cycles. On the other hand, there's a growing need for technology innovation to keep up with the requirements of increasingly diverse and demanding software applications. Can the semiconductor memory market, which has used the same basic DRAM cell technology for 40 years, respond with the needed changes?

These are some of the thoughts I came away with from last week's Denali (now Cadence) MemCon 2010, a one-day technical conference that attracted several hundred attendees. In this first of two postings, I'll look at what analysts had to say about the perpetual boom-and-bust cycles that mark the memory industry. In the second posting, I'll report on a "what comes after DRAM" panel that looked at upcoming technology challenges and possible solutions.

As is obvious from the recent purchase of Denali, memory is an important issue for Cadence. John Bruggeman, Cadence CMO, opened the conference by talking about the "application-driven world" portrayed in the EDA360 vision paper. "The memory subsystem has become a critical component, perhaps the critical component, in this new application-driven world," he said, noting that memory access time has become the major bottleneck for many software applications.

Perpetual Boom and Bust

Analysts came to MemCon with what you would think is good news - the good times are rolling again. Memory market analyst Lane Mason said that 2010 could be a record year for semiconductor memories - around $75 billion - and that the recovery from the 2008-2009 recession is "the most remarkable snap-back we've ever seen."

The bad news is that the Great Recession dinged the memory market to the tune of $30 to $35 billion. And another crash will happen again. "The elephant in the room is how long the good market will last before memory producers start making too much, demand falters, and prices plummet as they always have," Mason said.

Analyst Jim Hardy, director at Objective Analysis, talked in some detail about how the boom/bust cycles work. As demand grows, manufacturers over-invest in capacity. This boosts supply, and prices plummet. Then the manufacturers under-invest until demand catches up and there's another supply crunch. It's so predictable that Hardy has a date for the next price collapse - 2012.

Hardy noted that NAND revenue is growing faster than DRAM, but NAND prices will be more volatile. Still, he predicted that NAND will outpace DRAM by 2015 to become a $58 billion market. He also noted that DRAM manufacturing costs have been decreasing at a steady 30 percent per year. Unfortunately, price declines in a downturn can be as much as 60 percent per year.

Lest you think the industry would learn, Mason reviewed six previous "bust" cycles - 1981-1982, 1985-1986, 1990-1991, 1996-1998, 2001-1003, and 2007-2009. One outcome is consolidation; the long-term trend is that there will be only two or three major players in each memory market, he said. One reason for the trend towards big players is high depreciation costs, which can be as much as 70 percent of cost of goods sold for advanced fabs. "The thought of not running a fab 24/7 is unheard of," he said.

At one point Steve Leibson, MemCon 2010 chair (and now marketing director at Cadence) asked whether anything can be done to prevent the boom/bust cycles. No, said Jim Cantore, president and chief analyst at JLC Associates. "It's built into the system," he said. Why isn't China in the memory market? "I think they study history," Cantore replied.

Technology Changes Needed

Cantore talked about technology as well as market dynamics. "Main memory is not keeping up with system requirements," he noted. "By 2015 we'll have to close that gap in performance and bandwidth." One thing that will help is the expected DDR4 release in 2012. Given the high cost of advanced process nodes, Cantore also predicted the widespread use of 3D ICs with several stacked memory die and a logic die, especially where low power and form factor are critical.

I'll leave off with Cantore's comments for today and pick up later this week with a posting about the "what comes after DRAM" discussion. Meanwhile, MemCon 2010 presentations are available on line.

Richard Goering

 

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