will be under maintenance from Friday, Oct. 3rd at 6pm (PST) thru Sunday, Oct 5th at 11pm (PST). login, registration, community posting and commenting functionalities will be disabled.
Home > Community > Blogs > Industry Insights > user interview verification and integration of analog ip
Login with a Cadence account.
Not a member yet?
Create a permanent login account to make interactions with Cadence more convenient.

Register | Membership benefits
Get email delivery of the Industry Insights blog (individual posts).


* Required Fields

Recipients email * (separate multiple addresses with commas)

Your name *

Your email *

Message *

Contact Us

* Required Fields
First Name *

Last Name *

Email *

Company / Institution *

Comments: *

User Interview: Verification And Integration Of Analog IP

Comments(0)Filed under: DAC, SoC, Analog, IP, Mixed-Signal, mixed signal, EDA360, Gulati, Cambridge

Cambridge Analog Technologies is a provider of high-performance, high-precision, ultra low-power analog IP that is sold to designers of mixed-signal SoCs. It is challenging to design and verify this kind of IP in the first place, and the company faces the additional challenge of making it easy for its customers to integrate and verify the IP in the context of the SoC.

In the video interview embedded below, Kush Gulati, Cambridge Analog Technologies CEO, talks about his company's offerings, the need for integration-optimized IP, and what verification his company does and what its customers need to do. This interview took place at the Cadence booth at the recent Design Automation Conference.


If video does not launch, click here

Here are a few additional points not included in the video clip. Gulati said his company eases integration challenges by providing integration guidelines, extensive support, and training, with regular meetings "all the way to GDSII." He noted that getting analog IP to work in noisy digital SoCs is a major challenge, and that analyzing noise effects requires very long simulations. While much progress has been made with simulation speed, more is always needed. Substrate modeling is also becoming an important capability.

One point that emerged during this interview is that integration-optimized IP, a concept discussed in the EDA360 vision paper, needs to be developed for analog as well as digital blocks. In fact it may be even more important for analog, given the difficulties of integration into mostly digital SoCs. As Gulati said in the interview, "I think EDA360 is a great concept, inasmuch as it takes into account the ecosystem of SoC manufacturers and IP providers and EDA...I think it definitely can apply to analog/mixed-signal as well."

Richard Goering


Leave a Comment

E-mail (will not be published)
 I have read and agree to the Terms of use and Community Guidelines.
Community Guidelines
The Cadence Design Communities support Cadence users and technologists interacting to exchange ideas, news, technical information, and best practices to solve problems and get the most from Cadence technology. The community is open to everyone, and to provide the most value, we require participants to follow our Community Guidelines that facilitate a quality exchange of ideas and information. By accessing, contributing, using or downloading any materials from the site, you agree to be bound by the full Community Guidelines.