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Gary Smith at DAC: SoC Design Costs Will Come Down

Comments(2)Filed under: Industry Insights, DAC, SoC, Design, EDA360, Gary Smith, costs, cost

System on chip (SoC) design costs are out of control and headed towards $100 million, but there's relief in sight, according to analyst Gary Smith at a Sunday presentation before the Design Automation Conference (June 14-18). In most respects Gary's speech, titled "Don't Panic! SoC Costs Will Come Down," tracked very well with key points raised in chapter 1 of the recent EDA360 vision paper.

"The latest doom and gloom for the electronic industry is that design costs are out of control," Gary said. "And costs are out of control primarily in software." According to the International Technology Roadmap for Semiconductors (ITRS), he noted, it will cost $100 million to build an "average high-end SoC" by 2011. By 2012, Gary said, SoC software is projected to be a "$79 million problem." One consequence is that semiconductor startups will find it very difficult to get VC funding.

Gary then talked about "power users" (11 percent of seats) versus "upper mainstream," "lower mainstream," and "late adopter" users. Power users include companies like IBM, Intel, NVidia, and Qualcomm. They use the latest tools and process nodes. Upper mainstream users lag behind by 1-2 nodes and don't use the latest tools. Consequently, to achieve the same design, a power user will typically spend $10 million less than an upper mainstream user.

So far Gary's talk mirrored closely the first chapter of the EDA360 paper, which notes the upcoming $100 million SoC development costs, describes the explosive cost of software development, and talks about how EDA serves design "creators" much better than "integrators." Gary uses different terminology, but I think of the power users as primarily "creators" and the upper mainstream users as primarily "integrators."

Gary then expressed the view that mainstream users will either move up to become power users, or will drop out of design implementation altogether and buy only ESL tools. I would put things in slightly different terms. If we can better serve integrators through environments like the Open Integration Platform described in the EDA360 paper, then the upper mainstream (at least those who are primarily integrators) will be more empowered to build SoCs and may well buy a variety of EDA tools. In contrast to the "implementation" tools aimed at creators, these tools will focus more specifically at solving problems related to IP integration and cost/power/package optimization.

So how to fix the design cost problem? If we can get the cost down to $50M, Gary said, we can afford to do high-volume designs. If we can get it to $25M, better yet. In the near term, Gary said, virtual prototypes offer the most promise for cutting SoC design costs. This includes not only those used for software development, but a technology Gary calls the "silicon virtual prototype" that will enable RTL handoff, allowing "the resurrection of the ASIC business model."

"We need major innovations in software design tools and methodologies to keep Moore's Law intact," Gary said. The EDA and embedded software industries must work closely together, he said.

Gary concluded his talk by saying "all of a sudden I'm seeing major EDA vendors preaching the gospel, which I'm very happy to see." Amen, Brother!

Richard Goering

 

 

Comments(2)

By Gary Dare on June 18, 2010
Richard, thanks for summarizing Gary Smith's presentation on behalf of those who couldn't travel to DAC this year!
This is a great perspective from Gary, because high returns would be seen from improving design at the system level, which telescopes down into silicon implementation ... a message that he has pushed for over a decade, one that Cadence has recently re-framed in its EDA360 perspective.

By Gary Dare on June 20, 2010
While I wasn't at DAC, the message that I got from your report (thanks, Richard!) and others on Gary Smith's talk was that his original ESL message is being extended by consideration of the software aspects ... that 'electronic system level' leads to both hardware and software design. As you point out, much like the theme of Cadence's EDA360 dialog.  EDA support for such a process will need to evaluate both hardware and software choices for performance, etc.  Not just hardware, as most offerings provide.

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