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Q and A: How Silicon Realization Changes IC Design

Comments(0)Filed under: Industry Insights, DAC, EDA360, SoC Realization, Mehndiratta, Sandeep, Silicon Realization

As described in the EDA360 vision paper, Silicon Realization represents the creation of  IP blocks, ICs, or systems-on-chip (SoCs) ready for software integration. But how is it different from EDA as we know it today, what are the challenges, and what solutions are needed? Sandeep Mehndiratta, group director of solutions marketing at Cadence, answers these and other questions in the following interview.

Q: The EDA industry has supported silicon design all along. What's new and different about the EDA360 Silicon Realization concept?

A: What's different is that the bar has shifted. Today, engineers have to design a chip with integrated functionality that was formerly distributed over multiple boards. A single chip may include audio, video, touch sensors, ambient temperature sensors, and more. Multiple applications are running at the same time. Then there's a manufacturing aspect - you have to ensure high yield and make sure the packaging cost is within budget.

If you look at a datasheet for a chip, it talks about function, power, performance, and unit cost. Our customers have to ensure that their silicon meets all these goals. But the flows available today are still legacy design flows based on sequential optimization. Designers first integrate the functionality, then do mixed-signal integration and verification, then optimize for power, and then hand off to packaging. There are massive iterations throughout the design, verification and implementation phases. These iterations result in cost overruns, schedule overruns, and missed specifications.

The promise of Silicon Realization is concurrent, objective optimization for power, mixed-signal, performance, packaging, and advanced node enablement. It is based on integrated, interoperable flows.

Q: What are the requirements for Silicon Realization?

A: Silicon Realization is about design intent, design abstraction, and design convergence.

Design intent means having an early, unified representation of the specifications for  behavioral, timing, power, and electrical and physical aspects of the design. By capturing intent early, you address issues up front and reduce iterations. For example, common constraints between analog and digital flows cut implementation time and reduce verification cycles. Compliance and metric driven verification deliver predictable schedules and improve quality, while ensuring that unified power intent is enforced from system analysis to physical implementation.

Design abstraction is about using higher level views of the design's function, timing and even physical behavior to do early trade-off analyses, accelerate validation, and reduce iterations. It is about using wreal [wired real] models for analog blocks to run mixed-signal verification at digital speeds. It is about using rapid prototyping for digital architecture exploration and floorplanning.

The EDA360 vision talks about starting with the applications and operating system and moving down. Design convergence is about combining top-down design and bottom-up methodologies to enable early analysis and optimization, and avoid issues later in the cycle. Convergence is enabled through early power estimation and analysis, in-design electrical and physical sign-off, and early planning. IC/package co-design is a convergence story because you're abstracting and you're making a decision earlier in the design cycle.

Q: How is Cadence delivering, or promising to deliver, on these approaches?

A: There are many proof points in the Cadence flow that satisfy requirements for design intent, abstraction, and convergence. These include multi-objective, physically-aware optimization; power-aware IP reuse with macromodeling; metric-driven verification; accelerated mixed-signal verification; ECO automation; mixed-signal interoperability; IC/package co-design; and design exploration and planning.

To take a specific example, Virtuoso 6.1.4 and Encounter Digital Implementation System 9.1 have common rules and models based on the OpenAccess infrastructure, enabling digital designers to get a gray box representation of an analog model and vice versa.

Q: Silicon Realization has a strong mixed-signal message. Mixed-signal design has been around for years. What's new?

A: Customer challenges around mixed-signal design, verification, and implementation are accelerating and expanding to virtually every chip they are designing. Any time a chip does real-world data handling, designers need to do mixed-signal integration and verification. Many IP building block components today are mixed-signal in nature.

Our customers not only have to worry about the functionality and verification of devices -- they have to worry about integrating the analog and digital interfaces. And there are mixed-signal challenges around advanced process nodes. Driven by integration cost factors, RF blocks will be put on smaller nodes, where the chances of failure will be higher. Mixed-signal challenges are a common cause of silicon failures for IPs, ICs and SoCs.

 Q: The EDA360 vision paper talks a great deal about integrators. It's clear that Silicon Realization is aimed at IP creators, but does it also apply to integrators?

A: Absolutely. There is an industry shift from pure creation to creation and integration. The goal is to differentiate in core technologies and to reuse or source the non-differentiating parts. For integrators to do that within the right budgets, and be able to integrate and deliver solutions on time, they need new methodologies and IP that is ready for integration.

Look at power, for example. Lots of advanced techniques are being used in power optimization for IP. So you cannot black-box the IP just for function and timing - you need power-aware optimization. Similarly, if you wait for the entire SPICE representation of an analog component to be ready for mixed-signal integration, you may have issues with bugs that are found too late.

What integrators need is a representation that lets them integrate the design in multiple contexts. They need the ability to recognize multiple facets of the design intent including function, power, and timing. They need abstractions of blocks at a level where they can do concurrent design and handle ECO changes, and they need methodologies that allow them to do accelerated, parallel design verification and implementation. Silicon Realization addresses these needs.

Q: You talked about moving to a higher level of design abstraction. The move to TLM-based IP creation and integration is an obvious example for digital, but what about analog and mixed-signal design and verification?

A: Abstraction means the ability to represent the attributes of the design in a consistent form while it is still tied to the lowest level of granularity at which the design is defined. In the analog world, methodologies are evolving for abstraction. One example is wreal models. These models let you model voltages and currents in a digital context. You're abstracting the design representation and still doing accurate representations of the functional and electrical behavior of the circuit, without waiting for a full SPICE representation.

Another example of abstraction is capturing power intent of IP blocks using macromodels, enabling power-aware integration and verification. You can represent the embedded power behavior of the circuit using CPF [Common Power Format], which lets users model power supplies, multiple domains, and circuit inputs and outputs. Another example of abstraction is the ability to extract a full timing model from Virtuoso for an analog/mixed-signal block, so it can be used in full-chip static timing analysis.

Q: Verification has become a huge challenge for IC design teams. From a Silicon Realization perspective, what capabilities are needed?

A: There are two aspects to this. One is that functionality is expanding, and mixed-signal is a manifestation of that. We need to scale functional verification to apply techniques around metric-driven verification to the mixed-signal world, and do that without giving up performance. The other aspect is power. An industry study showed that 87 percent of design respins at 40 nm involved leakage problems. Power is becoming a central aspect of verification, and what's needed is a unified intent representation that starts at the IP level and flows into integration and verification.

Q: How is Cadence bringing the Silicon Realization message into the Design Automation Conference?

We will be demonstrating Silicon Realization solutions at the Cadence booth. We are also planning a Silicon Realization lunch panel Tuesday, June 15, from 11:30 am to 1:00 pm. A panel moderated by Cadence CMO John Bruggeman will include presenters from Cadence, GlobalFoundries, Rapid Bridge, and Qualcomm. They will discuss how to go from concept to silicon as quickly and cheaply as possible, while retaining the high quality that end customers demand.

Richard Goering



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