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Q and A: How SoC Realization Enables IP Integration

Comments(0)Filed under: Industry Insights, SoC, IP, EDA360, Open Integration Platform, bare metal, SoC Realization, Kapoor

Systems-on-chips (SoCs) are more than just silicon. In the EDA360 vision, SoC Realization refers to the development of complete SoCs along with "bare metal" (hardware dependent) software. In this interview Vishal Kapoor, vice president of product management at Cadence, describes SoC Realization with the silicon IP "stacks" and Open Integration Platform that enable it.

Q: EDA360 includes System Realization, SoC Realization, and Silicon Realization. What is the role of SoC Realization?

A: Silicon Realization is about getting a piece of hardware into a packaged chip. SoC Realization is the bridge between Silicon Realization and the application layer of System Realization. We're saying the SoC is not just a piece of silicon, but that it has an associated amount of software called "bare metal" software. This software presents the hardware to the application, allowing the application to have controllability and visibility into the hardware.

So, SoC Realization extends to the bare-metal software level. When you take that SoC and put it together with other SoCs, ASSPs, or custom chips onto boards and into a final enclosure, that completes the hardware story. When you bring in the OS, middleware and application parts of the software stack, the System Realization story is completed.

Q: How are you defining bare-metal software?

A: It includes the drivers, the hardware abstraction layer, and some of the monitoring capabilities. It's the software that allows controllability and visibility into the hardware.

Q: Why does SoC Realization go beyond silicon to include bare-metal software?

A: Because bare-metal software gives the applications controllability and visibility of the hardware resources of the system. In the past, you wrote code for a processor that controlled all the hardware resources. But in today's SoCs, there are many hardware resources and many subsystems. The hardware resources are distributed. You have to provide control and visibility into all the hardware resources without relying on the processor to do that.

Suppose an application tells the hardware to do a 3D rendering. If you haven't presented the hardware capabilities to the software layer, then the hardware becomes commoditized because the software just assumes the hardware can't do it. That's why the driver has an important responsibility.

Bare-metal software is thus a crucial part of the "application driven" vision of EDA360, in which software applications will be able to dynamically reconfigure hardware resources as they're needed.

Q: SoC Realization brings in the idea of an "IP stack" that includes a physical layer, design IP, verification environment, constraints, and driver software. Why is it important to provide such a stack, and who will supply them?

A: An SoC used to be 80 percent designed in house and 20 percent designed using external components. Now that ratio has flipped. When you get components from the outside, you have to make sure they work at different levels of abstraction. That's where the stack comes in. As you're building an SoC with more and more tiles from the outside, we're giving you bigger and bigger tiles rather than individual components you have to connect together with more putty.

Cadence has stated its intent to deliver IP stacks, focusing first on the I/O subsystem. An example is the recently introduced SuperSpeed USB 3.0 Host Controller.

Q: The EDA360 vision paper talks about integration-optimized IP. Can you give an example?

A: Let's say I'm a developer who needs to integrate USB 3.0 into a design. Traditionally I have to acquire a set of assets that allow me to embed USB functionality into the device. At the first level I take the PHY and the controller, which are usually sold separately, and integrate them. I add on the driver and integrate that. And then finally I try to make sure it all works together functionally as well as delivering the required performance. All of these efforts distract from adding differentiated value to other parts of my design.

With integration-optimized IP we supply a fully integrated and optimized stack that is ready to be placed into the developer's SoC design - eliminating all of the extra work I just talked about. This allows the developer to put time, money and effort into other activities to enable greater differentiation of the final design.

Q: Cadence has talked about the need to move to transaction-level modeling (TLM) for IP design and integration. How does that fit into the SoC Realization concept?

A: As you take more and more components into an SoC from the outside, and these components are more and more complex, there's a significant value in representing these components at a higher level of abstraction. As you follow a path from TLM to implementation, you gain greater clarity and speed for defining the top level, and provide a path to specific data based on your needs.

As you tie into System Realization, TLM allows you to run a fast and reasonably accurate representation of the hardware, so that software development can begin on a virtual prototype.

Q: Cadence announced the Open Integration Platform at CDNLive! EMEA in early May. What are its basic capabilities and what's really new compared to EDA today?

A: The first component is an integration design environment. While today's EDA environments are focused on creation, this environment evolves to support both creation and integration. Any time IP is created, it is created for easy integration.

The second attribute is a set of IP stacks that are optimized for integration. The third piece involves Cadence services, which have had a long history of doing projects for clients that integrate different pieces of IP into SoCs.

Q: What does "Open" mean in Open Integration Platform?

A: It means we are not restricting the source from which you get the IP. We're not talking about open source, we're talking about an ecosystem of companies that come together to provide the IP that's needed. The value that Cadence adds is making the IP integration optimized. The IP itself can come from partners, joint development, or in-house IP that we have. Several partners were announced in May.

Q: What will Cadence be showing with respect to SoC Realization at the upcoming Design Automation Conference?

A: Cadence has its own strategy for delivering on the "realizations" defined in the EDA360 vision paper, and we want to make sure that we clearly articulate to our clients what we can provide. We talked about our SoC Realization strategy at CDNLive! EMEA. At DAC, you're going to see more progress demonstrated at the SoC Realization level, as well as with System Realization and Silicon Realization.

Richard Goering

 

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