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UVM 1.0 EA Is Available – What This Means To You

Comments(0)Filed under: Industry Insights, Accellera, OVM, verification, Functional Verification, Verification IP, VIP, UVM

A milestone in functional IC verification was reached today (May 17, 2010) as Accellera released the Universal Verification Methodology (UVM) version 1.0 EA ("early adopter") to the verification community. Here's some background on how this happened, why it's important, and how it impacts current users of the Open Verification Methodology (OVM) and the Verification Methodology Manual (VMM).

During the past two years, the Accellera Verification IP (VIP) Technical Subcomittee has been working to drive the industry towards a single standard verification methodology based on SystemVerilog. That's because two different, incompatible formats have emerged. These are the OVM, backed by Cadence and Mentor Graphics, and VMM, backed by Synopsys. As a result, the reuse of verification testbenches and VIP has been difficult. To find a solution, Cadence, Mentor and Synopsys joined together in support of the VIP subcommittee.

Last year the VIP subcommittee released a Recommended Practices interoperability guide. It shows how VMM testbenches can work with OVM VIP, and vice versa. But the more ambitious mission has been to create a single SystemVerilog methodology standard with a common base-class library, and bring it to the IEEE for standardization. This effort became known as "UVM." Last December, the VIP subcommittee voted to make the OVM the basis of UVM.

A "Phenomenal" Standards Effort

The work done by the Accellera VIP subcommittee has been "phenomenal," according to Adam Sherer, product manager at Cadence and secretary of the VIP subcommittee. In most standards efforts, he noted, there is a "lowest common denominator" solution, but the verification experts who staffed the committee made it clear that wasn't going to happen here. The committee built a new standard in just five months.

And not just any standard, Adam noted - this is the first time that Accellera has created complex software for the industry to download and use. Normally Accellera, like other standards organizations, has produced reference documents. Offering software mandated new procedures for gathering requirements, building specifications, implementation, and testing.

Impact on OVM Users

Current OVM users have it easy. UVM 1.0 EA is essentially OVM 2.1.1 with a few additions. UVM 1.0 EA is a clean superset of OVM 2.1.1, and it offers backwards compatibility with OVM. Since OVM 2.1.1 is in production flows today, and anything that's been added is clearly identified in the release notes, the so-called "early adopter" release of UVM is really production-ready, Adam said. Cadence tools will support it immediately.

Most current OVM users will probably wait until their next project starts to move to UVM. One small difference is that base class names in UVM start with a "U" instead of an "O." Cadence will provide a script that can automatically make that change.

Callbacks are provided in UVM 1.0 EA. They're also in OVM 2.1.1, but not in OVM 2.0.3, which is still widely used. Callbacks enable testbench applications, such as scoreboards, to be alerted when events occur in the design or in the testbench itself. One VMM feature that was not part of OVM, and has been added to UVM 1.0 EA, is a "report catcher" API. This is a mechanism for filtering out types of warning messages that the user identifies as irrelevant.

Impact on VMM Users

The migration for VMM users is going to be more difficult. There are, however, ways to make the transition to UVM, and you can expect to see webinars, blogs and other documentation become available in the near future. VMM does support callbacks so that feature, at least, should be familiar in UVM.

Next Step - A Register Package?

There's still more work to be done, and the hottest topic right now, according to Adam, is identification of a UVM register package. In a testbench, the operating conditions of the design are set up through registers, and engineers need to know where the registers are, what the fields are, and how values are recognized and set. This is accomplished with a register package. Today, these packages are provided separately by EDA vendors.

How important is it? Verification consultant J.L. Gray ran a survey in his Cool Verification blog, and 57 percent of respondents identified a UVM register package as "critical." Adam observed that the IP-XACT standard developed by the SPIRIT Consortium, which has merged with Accellera, provides a good basis for supporting a register package, but will need some extension.

Other future topics include transaction-level modeling (TLM 2.0) functionality and support for multiple verification languages. But I think we can stop for a moment and appreciate how far the UVM standardization effort has gotten in such a short period of time.

The Accellera UVM 1.0 EA software is available without charge using the Apache 2.0 license.The release contains the UVM library, examples, the user guide (which is virtually the same as the OVM User Guide), the reference manual, and the release notes.

Richard Goering




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