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3D IC Standards – First, Let’s Define Our Terms

Comments(0)Filed under: TSVs, 3D ICs, TSS, Si2, Industsry Insights, Standards, stacked die, TSV

There's a lot of interest in 3D ICs these days, but there are many challenges to solve before 3D IC design can move into the mainstream. One challenge is the establishment of standards for design, modeling, and manufacturability. But the starting point is likely to be something even simpler - a dictionary that defines a common taxonomy for 3D ICs.

If we're going to talk about a new technology, we have to have some agreement on what we're talking about. What, exactly, is a 3D IC? Ask a dozen people and you might get a dozen different answers. Some people might say, "3D ICs have been around forever - we used to call them MCMs [multichip modules]." Others might define 3D ICs strictly in terms of through-silicon vias (TSVs), which is a new technology. When people talk about "3D ICs" these days, I generally assume they are referring to heterogeneous stacked die (more than just memory) with TSVs through active layers. But that's just a presumption - there's no standard definition.

 

Many other commonly-used terms lack standard definitions. This includes system-in-package (SiP), package-on-package (PoP), MCM, TSV, interposer, and others.

Dictionary is First Step

Last fall, the Silicon Integration Initiative (Si2) and the Global Semiconductor Alliance (GSA) held a workshop to define requirements for 3D IC design flow interoperability standards. "The first item that resonated with everybody is to come up with a dictionary," said Sumit Dasgupta, senior vice president of engineering at Si2. "Once we have a dictionary, we can at least have a taxonomy where we can exchange the same information. Right now, it's like four blind men trying to describe an elephant."

Workshop presentations mentioned other possible standards activities, including updates to APIs and databases such as OpenAccess; new standard interfaces for thermal and mechanical stress engines; a new standard for expressing thermal constraints; and 3D interface standards for package design systems. Presentations also discussed the technology and design challenges behind 3D ICs. Presentations from 19 organizations and companies, including Cadence, are available at the Si2 web site.

Samta Bansal, senior product marketing manager for Encounter Digital Implementation at Cadence, likes the idea of a dictionary. "The community has to get together and talk the same language," she said. "For example, in manufacturing, we talk about ‘via first,' ‘via last,' and ‘via middle.' I don't think everybody in the community has a clear idea of what these terms exactly mean and what their impact is. A dictionary can at least serve as a first reference guide."

Manufacturing and Test

Meanwhile, the 3D-IC Alliance is focusing more on the manufacturing side, and has released the Intimate Memory Interconnect Standard (IMIS) to standardize vertical interconnect requirements. The Alliance maintains a literature page with an updated listing of articles, blogs and publications on 3D ICs.

Another area calling out for standardization is 3D IC test. As described in a whitepaper from Asset Intertech, two emerging standards - IEEE 1149.7 compact JTAG and IEEE P1687 internal JTAG (iJTAG) - can be deployed together to embed test structures in 3D ICs.

But first things first. We can't have a useful 3D IC standards discussion if we don't agree on what a "3D IC" is.

Richard Goering

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