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Wind River Partnership Links Virtual Prototypes To RTL

Comments(1)Filed under: Industry Insights, Palladium, incisive software extensions, Simics, Virtutech, Intel, Wind River, Virtual platform, Incisive, Simulation, Simulator, virtual prototype, EDA360, emulator

There's an important message behind a partnership that Cadence and Wind River announced April 27 - virtual prototypes don't have to stand apart from the rest of the design flow. The partnership promises to build a bridge between virtual prototypes and the RTL implementation and verification environment, including simulation, emulation, and acceleration. It also raises the possibility of using virtual prototype models directly for implementation, and as I'll explain, may change the way some of those models are developed.

Some background is necessary to understand the partnership. In May 2009, Cadence announced a collaboration with Virtutech, then an independent company, to link the Cadence Incisive Software Extensions product to Virtutech's Simics virtualized system development environment. In brief, Incisive Software Extensions was extended to read Simics function calls, and to non-intrusively access the virtual prototype. As a result, software developers can have access to all the features of Incisive metric-driven verification - including verification plans, randomization, and coverage metrics - for debugging hardware/software interfaces and hardware-dependent software such as device drivers.

Building Tighter Links

So what's new in 2010? For one thing, the partnership is now with Wind River, which became an Intel subsidiary last year. After Intel bought Virtutech earlier this year, Wind River added Simics to its product line, which includes Linux and VxWorks operating system platforms and a comprehensive portfolio for embedded software development. The Cadence-Wind River partnership is the kind of collaboration that will be needed to enable System Realization as described in the EDA360 vision paper. The link between virtual prototypes and the RTL environment is an important step towards System Realization, which seeks to enable hardware/software platforms with complete software stacks up to the applications level.

At present, the partnership expands on the 2009 agreement in a couple of ways. First, Wind River and Cadence are demonstrating the use of the Cadence C-to-Silicon Compiler to synthesize Simics models into RTL. From there, the models can be brought into RTL simulation as well as acceleration and/or emulation with the new Palladium XP Verification Computing Platform. Secondly, transaction-based acceleration is now possible between Simics and Palladium XP. That means that RTL, SystemC, and Simics models can be co-simulated as software executes through a transaction-level testbench on a workstation.


Building on the 2009 partnership with Virtutech, the 2010 partnership with Wind River adds more links between virtual prototypes and RTL design.

 

There are various ways to use the new capabilities. Some components of the design could be placed in Palladium XP, while others remain in Simics, and the stimulus could come from embedded software directly connected to Simics. Or, stimulus could come through a JTAG port connected to target hardware. Or, it could come from a verification testbench in the SystemVerilog or e languages. A pure SystemC or C model can run directly with Simics, but if other languages are involved or detailed SystemC debug or analysis is required, it will be necessary to bring in the Incisive Enterprise Simulator.

Various co-simulation scenarios allow you to trade off speed and accuracy, but also require some thought. Simics typically runs in the hundreds of MHz, while Palladium XP runs in the 1-4 MHz range. Palladium XP, of course, is much more accurate. A very wide variety of speed/accuracy combinations is thus available.

High-Level Synthesis

The most interesting possibility, in my mind, is that of synthesizing Simics models into RTL code for implementation and verification. Since the Simics Device Modeling Language (DML) compiles to C, and C-to-Silicon Compiler can read C, in theory any Simics model can be synthesized once you provide constraints for timing, area and power.

In practice, high-level synthesis will probably work well for algorithmic models, but results are less predictable for Simics device and processor models. That's because these models are typically not created for implementation, and as such, may not be sufficiently optimized in synthesis for silicon implementation. One solution is to develop models that are more optimized for implementation, and another is to reuse the legacy RTL that is often available for devices and processors.

Is a virtual prototype-to-RTL flow important enough for people to start writing models that are targeted for eventual implementation? With a bridge in place, and with clear time-to-market benefits from the new flow, we believe the answer will increasingly be "yes."

An SCDsource article provides more information about the Simics-to-Palladium XP link.

 

Richard Goering

Comments(1)

By Bernard Murphy on May 13, 2010
Richard - no question EDA360 is on the right track. We are committed believers that the bridge from system to silcon must be supported through structured SoC assembly with views both down into the hardware realization and up into the bare-metal software level.
A very realistic realization of your concept to map virtual prototypes to implementation seems entirely feasible, through synthesis for some aspects of the design, but more generally through mapping to proven configurable (and static) IP, selected and analyzed in the implementation view for power, performance and area feasibility.
Verification is similarly a comprehensive validation of the driver-level against the real implementation through traiditional simulation methods, driven from the assembly platform hardware and register views, and the application level against the driver level through application validation on the virtual platform.
These trends are exactly what is driving our 1Team(R)-Genesis product line. We're happy to see that others agree!

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