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EDA Workshop: A Reality Check On 3D ICs

Comments(1)Filed under: EDA, EDP, Electronic Design Processes, Lim, IC, Williams, stacked die, 3D, Deokar, TSV

3D ICs are an attractive technology, but what will it take to make them successful? Presenters at the recent Electronic Design Processes (EDP) workshop didn't have all the answers, but they had a lot of interesting insights into how EDA tools and flows will need to change to support stacked die with through-silicon vias (TSVs).

 

Salvation for Moore's Law?

In the workshop's opening keynote address, entitled "An(other) Inconvenient Truth," Tom Williams (a well-known design for test expert, now retired) talked about some of the inherent problems with the "nanometer rush" fueled by Moore's Law. As we move to lower process nodes, he noted, there are increasing problems with Ioff current, power density, leakage, and variability. Gate utilization is declining at each new technology node, and increased costs mean that revenue will shrink if volumes don't double at each new node.

"More of Moore means more than just Moore," Williams said. "It needs some creative thinking in another dimension." That dimension, he suggested, is 3D. He said that 3D ICs will offer much easier analog/digital integration, smaller footprints, higher bandwidth, shorter global interconnect, better timing, and lower power.

But there's much to be done, he noted. One challenge is test, and the solution Williams proposed is built-in self test (BIST). 3D power analysis, thermal analysis, and floorplanning will become important as well. The bottom line: "The third dimension will keep Moore's Law alive and well."

Making 3D ICs Successful

Rahul Deokar, product manager for the Encounter Digital Implementation System at Cadence, offered a presentation entitled "3D ICs, are we there yet?" He noted that "cost is the new driver in today's world," and that moving an entire system to a new process node is risky and costly. With a 3D IC, he noted, you can still build your CPU on a low process node and keep analog and memory on a mature process node.

Much will need to change, however, in the EDA world, including new layout rules, a new backside layout layer, new floorplanning rules, and thermal and mechanical constraints. Customers are especially concerned about thermal issues when die are stacked on top of each other. "It's a heat pocket, and you've got to figure out how to release that heat,"  Deokar said.

There's more. Deokar outlined 3D IC design flow challenges including system-level exploration (how do you stack the die?), 3D floorplanning that optimizes TSV locations, placement and routing with TSVs, extraction and analysis across multiple die, and new approaches to design for test (DFT). He also stressed the need for a 3D ecosystem including IP providers and foundries. "Indeed it takes a village," he said.

Some Tough Challenges to Resolve

One thing that hadn't occurred to me is how big TSVs really are. Sung Kyu Lim of the GTCAD Laboratory at Georgia Tech illustrated that very dramatically in his presentation. The slide below shows that a TSV with landing pad and keep-out area is several times larger than gates and memory cells:

 

Lim went on to identify a number of issues with TSVs:

  • Because they're so large, TSV count is critical. As you use more TSVs the wire length goes up.
  • TSV location is critical. There's often a tradeoff between timing and manufacturability.
  • TSVs cause coupling. To reduce it, you can add more space to the keep-out zone, but then you add to area.
  • TSVs require design for manufacturability (DFM). They cause stress and CMP issues, but no litho problems, fortunately.
  • TSVs require DFT. Many questions remain here, such as how to test the TSVs in each die and how to provide power to each die.

It's still worth the effort, though. Lim spoke of a recent 3D IC with 64 processors that GTCAD recently taped out - possibly the first many-core 3D processor from academia. If you want to know more about TSVs, Lim published a recent article on the DAC web site that summarizes TSV-aware tool needs.

Other Voices

There have been some recent blogs on 3D ICs as well as EDP. Here's a quick summary:

Rahul Deokar posted a blog on his impressions of 3D IC discussions at EDP. Samta Bansal of Cadence recently wrote about 3D IC activity at the DATE conference in Europe. Clive Maxfield wrote about Cadence's approach to 3D ICs in a blog at Techbites.com.

Harry the ASIC Guy (Harry Gries) posted an interesting overview of EDP. I wrote an Industry Insights blog about an EDP debate on parallel programming for EDA tools. Main problem with EDP: Too much good stuff, too little time.

 

Richard Goering

Comments(1)

By UofTEng on April 26, 2010
The key issue of 3D IC design is how to optimize TSV placement. It the proper number of I/O pads are correctly converted to TSV, I/O power will be significantly reduced results in less heat dissipation. 2.5D design methodology should be adopted to maximize current SoC EDA advantages for 3D IC design.

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