Last month the SOI
Industry Consortium announced a "Ready
for SOI Technology" program with initial offerings of silicon-on-insulator
IP from ARM, IBM and Cadence. Since interest in SOI appears to be growing for
advanced process nodes, I thought it would be a good time to look at what
"ready for SOI" means with respect to IP, tools and people.
Last year I wrote a blog
that discussed the power advantages of SOI, so I won't repeat the details here,
except to note that the impetus for SOI seems to be shifting from high
performance to low power. While SOI claims to provide a performance improvement
of up to 30 percent versus bulk CMOS, it can also provide a power reduction of
up to 40 percent at an equivalent level of performance. Thus, the SOI
Consortium sees an opening to bring SOI, already successful in the server and
gaming markets, into new marketplaces.
But first, there must be an infrastructure that supports
SOI, and it must have three elements.
"SOI Ready" Libraries
We're assuming for the sake of this discussion that an SOI
foundry process is available (and it is - from IBM). Like any new process, SOI
requires IP, starting with standard cells, I/Os, and memories. For some time ARM
has offered such libraries for the 45 nm IBM SOI process - in fact, Cadence validated
the libraries last year. What's new is that the ChipEstimate.com site now
has an SOI portal that lists
"SOI ready" IP, including ARM standard cell libraries. Here you will also find:
ADCs and rad-hard cell libraries
- A long
list of IBM SOI IP
PCI Express 3.0 PHY
So what makes IP "SOI ready?" Like any hard IP, it must
follow the process rules in the process design kit (PDK). There are a few
things that are different from bulk CMOS. For instance, SOI transistors have
higher drive currents, making it possible to use smaller transistors.
What concerns most novice SOI designers, however, is
modeling the history effect. Because of the floating body
transistor effect, the same transistor will switch differently depending on
recent switching activity. The good news is that this is handled at the library
level and is basically invisible to designers. One thing that's a little
different is that you will have two timing libraries for each process, voltage
and temperature (PVT) corner - Max-SOI where slower delays are needed, Min-SOI
where longer delays are needed.
"SOI Ready" EDA Tools
Timing and signal-integrity tools need to work with the two
libraries mentioned above. Timing accuracy is the same as for bulk CMOS, with
minimal flow impact. Signal integrity analysis for SOI is a bit more complex.
Because of the history effect, the floating body can have a large swing, and
this can cause some uncertainty in drivers and receivers. A signal integrity
tool must be able to model the history effect in the presence of noisy nets. The
Digital Implementation System offers these capabilities.
"SOI Ready" People
Preparing designers for SOI is not difficult - in fact, advocates
say, a good start takes only a few hours.
The SOI Consortium is offering a Jump Start Training session
Wednesday, April 28 at Cadence San Jose headquarters, from 9:30 am until 3:00
pm Pacific. It can also be accessed as a live and recorded webcast. Registration
is free and open to anyone.
"In about four hours, we can put forward the information
that designers need to know to get started in SOI," said Jeff Wolf, director of
membership development at the SOI Consortium. The fact that this can be done in
four hours (plus lunch) "dispels concerns in the industry that people have to
have experience in SOI to design successfully in SOI. That's not the case,"
If you're curious about SOI, come by or log on!