You may think that FPGAs are "easy" to design compared to
ASICs or SoCs. But just wait until you try putting a large, complex FPGA on a
printed circuit board. Several things could go wrong - including pin
assignments that don't work in the board layout, signal integrity problems on
the board, and parasitic package inductance.
Fortunately, help is available for each of these problems.
Cadence recently acquired FPGA/PCB "co-design" technology that automates and
optimizes pin assignments, and PCB signal-integrity software is widely
available. Meanwhile, FPGA vendors have made progress in solving some of the
packaging problems that were more prevalent 5 or 10 years ago.
The reason problems have emerged in the past is that FPGA
design is traditionally isolated from PCB design. Hemant
Shah, director of product management for the Cadence Allegro PCB and
FPGA products, noted that FPGA designers typically do their design with no
knowledge of the board, and then toss it "over the wall" with fixed pinouts. A
hardware designer breaks complex FPGAs into multiple schematic symbols, and a
PCB layout designer then tries to lay out the board.
In short, it's a serial, blind, iterative process. When pin
assignments are not optimized, the designer has two undesirable options:
the pinout and spend extra time routing the board and/or add layers, which
adds to the overall cost of the product.
- Kick the
FPGA design back to the FPGA designer, who has probably gone on to another
project by now, and who may have to resynthesize the FPGA if pin
assignment changes are extensive.
Hemant defines co-design as "a way to bring FPGA and PCB
design into one environment." The 7Circuits technology developed by Taray Inc. accomplishes this by providing
automated, placement-aware I/O pin assignments for FPGAs. Cadence last year
rolled out Allegro and OrCAD FPGA
System Planner, based on the Taray technology, and in March of this year Cadence
acquired Taray. A recent Cadence
Community blog by Jerry Grzenia provides more information about the
technology and includes links to external blog and news coverage about the
There's another problem that could use some "co-design"
help, however. FPGAs allow designers to assign different voltages, drive
strengths, and slew rates to pins. If there are too many high-speed signals,
the result could be ringing and crosstalk on the board. FPGA System Planner can
help, Hemant noted, by adhering to FPGA vendor guidelines such as not placing
too many high-speed signals close to each other.
PCB SI, meanwhile, offers signal-integrity analysis at the board level.
"One of the future things we will work on is integrating our SI [signal
integrity] process with the pin assignment process," Hemant said.
A third problem is that parasitic package inductance can
cause functional failures due to Vcc and ground bounce. This was a real concern
six years ago, when I wrote an article entitled "When
bad packages kill good PC boards" for EE Times. At the time, designers were
experiencing product delays and board respins. In one example in the story, an
FPGA designer experienced a 9-month delay and re-engineering costs of $20
million due to an FPGA package that didn't work on a high-speed board. In
another example, a company went out of business.
My understanding is that FPGA vendors have since responded
to this challenge and greatly improved their packaging and their documentation.
Meanwhile, Allegro PCB SI takes package inductance into account.
If you're designing an FPGA, the last thing you want is to
find that it doesn't work on the board without an expensive and time-consuming
re-design. FPGA/PCB co-design technologies can reduce that worry.