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ISQED Keynote: Putting Some Numbers To Cost-Aware Design

Comments(1)Filed under: Industry Insights, chip estimate, Incyte, TLM, SoC, ISQED

We've all heard about the escalating costs of system-on-chip (SoC) development. But what are the costs, and what are the potential savings? Steve Glaser, corporate vice president of strategic development at Cadence, filled in some of those numbers at a keynote speech March 24 at the International Symposium on Quality Electronic Design (ISQED).

Steve talked about both design costs and unit costs, and identified "best practices" that can help reduce both. He also discussed the cost of delay (getting to market late) and the cost of failure (such as respins). "We're dealing with the exploding costs of design and trying to get to the point where we can create a very predictable and profitable chip design industry," he said.

First, the bad news

Steve first presented some information about design and unit costs. It comes from various sources, including customers and analysts:

  • SoC development costs are reaching $50M to $100M. Some customers say the cost is doubling with each new process node.
  • A three month delay in a "medium moving" market can cost nearly $20M.
  • Mask costs will soon be $6M. Considering additional costs, a respin may cost $5M to $10M on top of a six month delay.
  • Increasing levels of power can cause a 4-10X incremental cost increase in packaging. In some cases the cost of the package exceeds the cost of the die.
  • Test can take up 15 percent of the total unit cost.
  • Mixed-signal integration problems cause 30-50 percent of respins.
  • Silicon IP royalties can exceed 15 percent of the cost of the chip.
  • The cost of designing silicon IP into an SoC can be 2-3X the cost of buying the IP itself. The cost of IP integration is rising dramatically.

The good news - best practices can help

Design and unit costs can be significantly managed by bringing "best practices" into IP creation and SoC integration early, Steve said. Some specific suggestions are as follows:

  • Start with chip planning that includes an economic cost analysis along with a technical analysis. (Note: Cadence Incyte Chip Estimator provides this capability).
  • View design differently. Adopt an "integration centered view" and find ways to lower risk and cost of IP integration.
  • Leverage an IP ecosystem with multiple sources. Optimize and track cost of IP selections.
  • Create IP that is "integration ready" so it will fit into a "much more automated SoC integration process."
  • Instrument IP so integrators can thoroughly test it in the context of the SoC.
  • Develop IP at the transaction-level modeling (TLM) level to "lower the cost of integration and improve the way reuse is done."
  • Lower packaging cost with IC/package co-design.

Finally, some good numbers

Steve provided a few examples of the time and cost savings that are possible through good design techniques:

  • The right mix of technologies can lead to a 10-15 percent die size advantage or a 5-10 percent performance advantage.
  • Techniques such as test vector compression can reduce tester time by 2X. Failure analysis costs can be reduced by 30-50 percent.
  • Integration-ready IP, in combination with TLM, can result in a 30 percent improvement in the time and cost of SoC integration and lower the cost of IP verification by 30-50 percent.
  • A 10X time reduction in some of the steps of SoC verification is possible.
  • Low power is really an SoC integration problem, and "best practices" can reduce low-power integration time by 20 percent.

One of my more popular blog postings last year suggested that SoC development costs are chronically underestimated. If that's the case, the kind of information that Steve presented in his keynote can only help.


Richard Goering


By Ramesh Dewangan on April 3, 2010
Thanks for a concise summary up to the point!
I completely agree the IP quality and issues in SoC integration are indeed resulting in skyrocketing SoC development cost. and indeed, best practices can help.
The best practices for IP to be "integration ready" includes making sure IP is optimized for low power, high test coverage, clock structures and timing at RTL development stage, rather than waiting for killer issues to surface at late implementation stages. For externally supplied IP's, you have to analyze the SoC adaptation risks before integration.  Atrenta SpyGlass platform provides this capability.
I have one more data to add for "some good numbers". We have found that early implementation-aware analysis by RTL designers and SoC integrators can result in over 10X productivity boost for platform-based design Methodology.
Mixed-signal integration is indeed increasingly becoming a challenge. Again, what is needed is an early analysis to identify issues that can be fixed upfront.

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