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SystemC AMS – A New Proposal For Mixed-Signal Verification

Comments(1)Filed under: Industry Insights, SystemC, OSCI, Virtuoso, Mixed-Signal, AMS, Incisive

In an effort driven by European semiconductor companies and universities, the Open SystemC Initiative (OSCI) last week announced the first version of the SystemC analog/mixed-signal language standard, AMS 1.0. Since Cadence is the industry leader in mixed-signal design and verification, and is strongly promoting a transaction-level modeling (TLM) based design and verification flow on the digital side, it's natural that folks at Cadence would take an interest in this development.

The message I get from our mixed-signal team is that while it's too early to speak of any potential support plans, Cadence is watching this development carefully and is seeking to learn more about the proposed standard and its current and future applications. We are reviewing closely the use of SystemC AMS, how it compares to other mixed-signal behavioral modeling approaches, and what the level of customer interest is.

Some background and commentary about SystemC AMS follows.

What it's all about

With increasing analog and mixed-signal content on systems-on-chip, design teams are looking for faster ways to run system-level simulations. They also need to incorporate mixed-signal functionality into system-level design and architectural exploration. Spice and Fast Spice are too slow for full-chip, top-level verification, and even languages like Verilog-AMS can pose a performance bottleneck.

According to the OSCI announcement, SystemC AMS extends the SystemC class library to provide functional modeling, architectural exploration, virtual prototyping, and integration validation for "embedded analog/mixed-signal systems." The extensions are intended to help engineers understand the interaction between hardware/software and mixed-signal subsystems at the architectural level.

A SystemC AMS whitepaper points out that system-level tools such as Simulink are often used for functional modeling but don't target architecture. It adds that Verilog-AMS and VHDL-AMS don't support hardware/software co-design at a high level of abstraction, and that co-simulation that mixes SystemC and Verilog-AMS or VHDL-AMS does not provide sufficient performance.

The whitepaper describes three types of SystemC AMS extensions:

  • Linear signal flow (LSF) models instantiate signal flow primitives such as adders, integrators, or transfer functions. They require a linear differential equation solver.
  • Electrical linear networks (ELN) instantiate predefined network primitives such as resistors or capacitors. They also require a linear differential equation solver.
  • Timed data flow (TDF) models consist of modules that are connected to signals using TDF ports. They accelerate data flow simulation by using static scheduling that is computed before the simulation starts.

The SystemC AMS 1.0 language reference manual (LRM) and associated documentation can be downloaded from the OSCI web site. Meanwhile, a 2009 article by Martin Barnasconi of NXP, OSCI AMS working group chair, provides more detail about modeling formalisms. The article notes support from NXP, STMicroelectronics, and Infineon in addition to several universities.

Questions and commentary

The basic idea behind SystemC AMS is right - mixed-signal design and verification need to move to higher levels of abstraction in order to run much faster. "When we talk about a system strategy, we need to make sure we include analog," said Andreas Kuehlmann, director of Cadence Research Labs. "To simulate any functionality, you need to simulate analog components together with software, processors, DSPs and so on."

There are, however, a number of practical questions, such as what one can and cannot do with transaction-level modeling in the analog world. Another question is what capabilities SystemC AMS might provide compared to other analog modeling approaches for high level design and verification, like Verilog-AMS wreal and VHDL real, and mixed language approaches like the combination of SystemC with Verilog-AMS/VHDL-AMS in a true mixed-signal simulator.

As noted in a recent whitepaper, real number models can represent analog behavior in a digital context, and the Cadence Incisive Enterprise Simulator can then run wreal and real models in a pure digital environment with all the advantages of high performance and metric-driven verification. Virtuoso AMS Designer can deal with mixed-language scenarios including SystemC, Verilog-AMS, VHDL-AMS, and Spice, providing a smooth path down to transistor-level implementation if needed.

So far, most of the push behind SystemC AMS has come from a few large European semiconductor companies, especially NXP, and academia. Now that the standard is out, will the interest extend more broadly? "As part of our interest in system-level analog modeling, this [SystemC AMS] is one of the options we will carefully monitor," Andreas said.

Feedback from analog/mixed-signal designers is very welcome!

Richard Goering

Comments(1)

By Yaseen Zaidi on April 30, 2010
We have worked out a solution consisting of high level simulation using Timed Data Flow Model of Computation in SystemC AMS and Cadence Incisive. We use our setup for cosimulating implementable models in Cadence IUS with the SystemC AMS specification models. Please check "Fast and Unified SystemC AMS - HDL Simulation" for rationale,  "On Mixed Abstraction, Languages, and Simulation Approach to Refinement with SystemC AMS"  for simulation based digital model refinement and "Analog Behavior Refinement In System Centric Modeling " a solution for cosimulating analog models with SystemC AMS. The scheme uses PLI interface for accessing simulation data. Once VHPI-AMS has been approved by IEEE and implemented in Incisive we would be able to directly probe continuous time nets. Until then analog event based modeling and conventional real valued discrete time object access is the solution.
Yaseen Zaidi

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