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ARM AMBA 4 Protocol And VIP – A Closer Look

Comments(0)Filed under: Industry Insights, ARM, specman, Incisive, VIP, AMBA, AMBA 4

ARM last week announced the first phase of its AMBA 4 specification, and Cadence simultaneously released Incisive verification IP (VIP) for the e language and SystemVerilog. So why is ARM releasing AMBA 4, what's in the two phases, and what's in the VIP? To get a closer look at what's in the AMBA 4 specification I talked to Keith Clarke, vice president and general manager of Fabric IP at ARM's Processor Division.

The widely-used AMBA 3 spec has been around since 2003, and it was time for an upgrade, Keith said. He noted that AMBA 4 was developed in conjunction with some 35 partners, including Cadence. A big motivation, he said, is the increase in performance of processor cores, as well as the ability to place multiple cores on SoCs and to support many different functions on a chip.

Additionally, the phase one release that was disclosed last week adds new support for FPGAs. Phase one includes the AXI4, AXI4-Lite, and AXI-Stream protocols. The phase two release, which will be disclosed later this year, will bring in features that will help users develop and program multicore SoCs.

Pete Heller, product line manager for VIP at Cadence, said he is "definitely seeing interest" among the customer base for AMBA 4. "The traditional mobile guys are currently planning their roadmaps for it," Pete said. What's attracting customers, he said, is increased performance, along with a hoped-for power savings.

AXI4 Protocol

AXI4 is an incremental and backwards-compatible update to AXI3 that improves performance and interconnect utilization for multiple masters. It supports burst lengths of up to 256 beats (data packets). Previous support only went up to 16 beats. "We don't foresee ARM processor requests for 256 beats of data, but we do foresee certain types of masters, in certain types of applications, that do need these long transactions of data," Keith said. An example, he said, could be a data interface in a networking application.

AXI4 also adds quality-of-service (QoS) signaling and support for multiple-region interfaces.

AXI4-Lite Protocol

This is a subset of AXI4 designed for communication with simpler, smaller control register-style interfaces. It can reduce the number of wires required to access "peripherals that have simpler needs." While designed with FPGAs in mind, "there is nothing to stop it being used for SoCs," Keith said.

In this protocol, all transactions have a burst length of one, all data accesses are the same size as the width of the data bus, and exclusive accesses are not supported.

AXI4-Stream Protocol

This protocol, unlike AXI4-Lite, is not a strict subset of AXI4. Designed primarily with FPGAs in mind, it aims to greatly reduce signal routing for unidirectional data transfers from master to slave. The protocol lets designers stream data from one interface to another without needing an address, Keith said. It supports single and multiple data streams using the same set of shared wires.

AMBA 4 Phase Two - Simplifying Multicore SoC Design

ARM is not saying much about AMBA 4 phase two now, but the company has noted that it will provide hardware support for cache coherency and message-ordering barriers. By putting more capabilities in hardware, AMBA 4 will simplify multicore programming. Keith said phase two will "have quite a lot of new technology for coping with multi-master systems."

VIP Support

Cadence Incisive VIP support is "really important," Keith said. "Cadence announcing so quickly is really good news for our customers who want to get a start on designing with AMBA 4." Verification IP, Keith noted, is increasingly important because "the complexity of devices has gone up, and people need to know when they attach various design IP blocks together that they are actually talking the same language."

Pete Heller said that the Cadence AMBA 4 VIP is currently available as part of an early access program for customers. It will be in production later in the year. In addition to the  testbench VIP that is available today, Cadence will also provide assertion-based VIP for formal verification and transaction-based VIP for system-level verification. The VIP is OVM-compliant and will include the Cadence Compliance Management System (CMS), which supports verification planning and metric-driven verification.

Pete noted that Cadence AMBA 2 and AMBA 3 VIP has nearly a 10 year track record and has been used in well over 1,000 projects, and he said Cadence is regularly working with ARM to ensure the highest quality and to support phase two of the AMBA 4 release with VIP. A Team Specman blog has more details about the AMBA 4 VIP and tells how you can request early access.

 

Richard Goering

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