Home > Community > Blogs > Industry Insights > q amp a new challenges new solutions in ic implementation
 
Login with a Cadence account.
Not a member yet?
Create a permanent login account to make interactions with Cadence more conveniennt.

Register | Membership benefits
Get email delivery of the Industry Insights blog (individual posts).
 

Email

* Required Fields

Recipients email * (separate multiple addresses with commas)

Your name *

Your email *

Message *

Contact Us

* Required Fields
First Name *

Last Name *

Email *

Company / Institution *

Comments: *

Q&A: New Challenges, New Solutions In IC Implementation

Comments(0)Filed under: Industry Insights, DFM, Encounter, CPF, SoC, digital implementation

Advanced nodes are raising tough new challenges for analog/mixed-signal and digital IC implementation, according to David Desharnais, group director and product manager for implementation at Cadence. In this interview, he notes where IC designers are struggling and succeeding, and describes Cadence's 2010 strategy to help make customers more productive and profitable.

Q: David, what does your job at Cadence involve?

A:  Every day I get to work side-by-side with the sharpest minds in the world of electronic design - people who are working on designs and design solutions for the biggest, most complex chips on the planet, which ultimately find their way into the coolest products and gadgets that change the world in which we live.  I get to be in the center of all the action, with customers, R&D, field operations, and partners - right where I want to be.

Officially, I lead product management and marketing for our digital, full custom, and analog design, implementation, and signoff verification offerings.

Q: What are the biggest customer challenges in IC implementation?

A: When you clear away all the fancy jargon and speak in everyday language, there are really two main things designers and their companies are concerned about today - how to be more efficient and effective in the design of their chips, and how to make the most money from the chips they choose to make.  Simply put, it all boils down to productivity and profitability in the end. 

Companies are making fewer but significantly bigger bets on the designs they target.  It used to be that companies would do 10-12 SoCs, hedging with the expectation that only a handful would have reasonable-or-better market success. Today these same companies are only targeting 2-3 SoCs, and it has become a very expensive proposition.  The success or failure of these SoCs can mean the success or failure of the enterprise itself.

As a consequence, these 2-3 designs are insanely large and complex - from the loads of functionality that has to be shoehorned onto them, to the advanced process nodes used to hit aggressive area or performance targets.  Getting to the point where you have the most competitive and differentiated die-size, performance, power, and yield for an SoC is a Gordian Knot that somehow engineers need to find a way to cut through.

For the implementation engineers, it's a really crazy time. The shrinking of process nodes and the sheer number of gates they have to deal with on a single SoC can really throw a wrench in the works if they aren't prepared for it. New and more severe factors come into play that design engineers traditionally didn't have to worry about, like how to architect the clocks when the size of the chip requires 2-3 clock cycles to traverse it, or how to optimize interactions of multi-mode, multi-corner timing, power, signal integrity, and DFM [design for manufacturability] in parallel.  Optimizing these things sequentially becomes a whack-a-mole situation.

Then there are things like how to deal with parasitics from the board and/or package and how they impact the silicon and vice-versa...and who's going to make sure that all the team members are compliant and aligned.  The list goes on, but it comes down to about a 10X increase in complexity for each major node transition. 

Q: Does this complexity call for a higher level of collaboration?

A: I would say there is a bit of a paradox happening right now.   To improve productivity, collaboration is vitally important.  However, the harder the problem or challenge, the worse the quality of communication seems to be.  You would want the opposite to be true to solve problems in a more cohesive way. But, when you have a team in Texas and a team in India and a team in Europe all working on various blocks of an SoC, it is non-trivial. 

Things have to be done differently than in the past.  Flows have to be very coordinated, unified standards must be applied, and full transparency is needed across all the pieces.  Otherwise what you have is inefficiency and waste.  Complexity has compounded in a very systematic way.

Q: What is Cadence's strategy for helping customers with productivity and profitability?

A: To reign in the productivity crisis, we need to help engineers harness complexity. One approach we've taken is through recommended design flows and methodologies we call Foundation Flows. Our approach is to bring downsteam intelligence up front in the design process and to provide tight linkages, out-of-the-box scripts, and visibility from the system level all the way down to final silicon.  Besides integration, we are also focused on establishing better handoff points across the flow, data abstraction, and overall simplification - like reducing the number of keystrokes or decisions that designers have to make in the course of a design.  All this is done so designers can move their low-power or mixed-signal SoC to the next process node with as few barriers as possible.

When it comes to profitability, our focus is to help customers create the most differentiated silicon possible, getting them to market in a predictable manner, and achieving the highest-yielding parts. For example, when we help a customer gain an extra 3-4 points in yield on a high volume part, by showing them how to optimize for DFM and yield right there in the design cockpit well before silicon, this can make multiple millions of dollars in difference to their top-line revenue, and it carries straight through to their bottom line profitability. 

Design cycles that used to be 18 months or 2 years are 6 or 9 months now. And the silicon has to work and work well. If you miss the window, you miss it completely.

Q: What are you seeing in terms of adoption of advanced nodes? Are customers moving on or staying put?

A: We see a cautious approach by the industry. The bulk of the market is still at 130 nm or 90 nm, but definitely people are starting to move. Every conversation I have with customers today includes advanced nodes and DFM - 40 nm or 32/28 nm, and more recently even 20 nm. These kinds of designs can run into the $60-$100 million range, so there is a definite gut check that happens before taking the plunge.

Customers want to know what to expect in terms of additional overhead they have to take on, compared to the benefit they hope to get.  On top of this, they have to find enough of a market to give them upwards of 80 million units to support that kind of investment. This kind of volume typically means consumer, which also means advanced node, mixed-signal and low power. Companies serving the consumer market are the trailblazers as you might expect.

Q: There's been much talk about 3D ICs with TSVs [through silicon vias]. Are you seeing customer interest, and if so, for what types of applications?

A: Yes, definitely. It's a very exciting area. Customers are producing test chips and production designs with TSVs already, and we have had longstanding partnerships with foundries and heavyweight customers in this area going on for 3 years now.

3D itself is not new. It's been done for years. However, 3D with TSV is new and the projections for growth in this area are high.  A key driver is that a 3D IC gets you a better form factor than a traditional side-by-side SiP, and brings significant advantages in performance, low power, and time-to market. A 3D IC approach also lends itself very well to design reuse and derivative designs.

Consumer electronics, wireless communications are by far the heavy users for 3D ICs, but we also see customers in other applications, such as bio-medical devices and automotive, moving to this technology now.

Q: What's been successful with low power design, and what remains to be done?

A: We have made great strides in low power, and we very much pioneered low power automation for the EDA industry. Every piece of our flow entirely supports and comprehends Si2's CPF [Common Power Format] today, and over the past two years we've seen literally had several hundred designs tape out using the Cadence Low Power Solution.  Along the way, we established mature, high-quality support for the various low-power techniques in broad use in the industry, and we have automated advanced low-power techniques like multiple supply voltages, multiple power domains, power shutoff, dynamic voltage and frequency scaling, and disjoint power domains as some examples.

Going forward our objective is to extend our leadership in low power, and we'll provide even more aggressive innovations like mixed-signal, variation-aware low power support, and enhanced thermal analysis.

Q: How will Cadence move forward on mixed-signal SoC implementation?

A: This is a core strength for Cadence. We have the technology, flows, expertise, and a significant user base that has been taping out these kinds of designs for over 20 years, and we continue to set the pace for new developments. We handle all aspects - design, verification, and implementation of mixed-signal SoCs.

With our latest release of Virtuoso [IC6.1.4] alone, customers are seeing upwards of 30% improvements in productivity.  But mixed-signal design is not just about analog or full-custom design -- it requires strong digital technology as well.  And the convergence of our digital [Encounter] and analog [Virtuoso] platforms drives many new opportunities for efficiencies across a mixed-signal flow.  Things like mixed-signal floorplanning, block and chip-level electrical analysis, substrate analysis, late-stage ECOs, unified constraints, and usability become very straightforward when you integrate the analog and digital design, implementation and verification worlds together.  That is very important for our customers and the industry overall.

Q: There are some new competitors in the analog/custom space. How will Cadence maintain its lead?

A: We are experts when it comes to analog and full-custom design, and we got this way from working with leading edge companies around the world to achieve technology breakthrough after breakthrough for well over 20 years. Every significant design in the world today uses Virtuoso.  We have taken this experience and have folded this knowledge into our tools.  We never stop innovating here.  It's in our DNA. 

For example, we recently reinvented our entire analog/full-custom suite of tools from schematic capture, environment, layout, automatic routing, and chip-finishing with Virtuoso 6.1, and customers are experiencing a massive difference in productivity and capability right out of the box.  There is a lot you can do when you know everything about the transistor -- how to build it, model it, simulate it, and connect it, particularly in the context of mixed signal SoCs.  We also constantly track flows and metrics with our major customers and use the results to further enhance productivity and the user experience.

Competitors will have to walk before they run. If customers want a place to walk, okay - but we're light-years beyond that, and from what we see, designers cannot afford to erase a decade of advancement in analog/full-custom design automation, even if it is free.

Q: Cadence recently announced Encounter 9.1. What's special about that release?

A:  Last year we introduced a completely re-architected digital implementation product line called Encounter Digital Implementation [EDI] System.  This has really been a hit with customers.  Our newest release of EDI System - 9.1 - builds on this very high-capacity, multicore, integrated infrastructure, and adds much more. 

We consider EDI System 9.1 to be our "productivity" focused release, bringing higher capacity, performance, and usability, along with a full suite of integrated signoff capabilities for timing, signal integrity, power, extraction, and DFM.  Heck, even the user-interface has been completely rebuilt from the ground-up and now adds many analog-style capabilities to address the requirements of very sensitive, high-speed clocks and signal nets that take on more and more analog characteristics as the process nodes shrink. 

In EDI System 9.1 customers will find that we've built manufacturing and signoff intelligence into what a designer does by default, so the quality of results are significantly better.  Also there is some very exciting technology around design exploration and automatic floorplan synthesis.  Not only can a designer can give the tool some criteria, and it will automatically build a good floorplan that attempts to meet the criteria -- it will actually leverage our multicore backplane to automatically create multiple permutations of floorplans, and rank and rate them from best to worst based on the criteria set.  Our customers tell us that this capability alone can take months off of the time it normally takes to arrive at an optimal floorplan.  Now that's what productivity is about, right? 

Q: What do you see as the most exciting trend in implementation right now?

A: I think the most interesting trends are in 3D-IC and in the bringing together of analog and digital design to make mixed-signal SoCs. 

A good friend told me once that doing analog design is like doing surgery.  The surgeon has to do it all very hands-on, methodically, and precise, and take the time to get it right.  Improvements come in the form of new tools, and better methods to drive more efficiency and performance without sacrificing the quality.  Conversely, doing digital design is like being a race-car driver - it's all about performance, timing, and breaking all the rules you have to, in order to get to the checkered flag.  As process nodes shrink the racetrack turns from a nicely paved road to a bumpy dirt road.  Improvements come in the form of absorbing the shocks and putting on meatier tires and heartier equipment, and tweaking the driving style to still win the race.  

If you follow that analogy so far, then the punchline is that designing today's mixed-signal SoCs is like asking that surgeon to jump in the racecar and do surgery while going 200 mph down a bumpy dirt road.   It's a problem the customers are trying to solve. Design, implementation and verification across analog and digital boundaries can be tripping points for customers. The most exciting thing for me is the opportunity to tie all these together.

 

Richard Goering

Comments(0)

Leave a Comment


Name
E-mail (will not be published)
Comment
 I have read and agree to the Terms of use and Community Guidelines.
Community Guidelines
The Cadence Design Communities support Cadence users and technologists interacting to exchange ideas, news, technical information, and best practices to solve problems and get the most from Cadence technology. The community is open to everyone, and to provide the most value, we require participants to follow our Community Guidelines that facilitate a quality exchange of ideas and information. By accessing, contributing, using or downloading any materials from the site, you agree to be bound by the full Community Guidelines.