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DVCon Panel: Three Ways To Minimize Verification Effort

Comments(0)Filed under: DVCon, SystemC, TLM, verification, Industsry Insights, MDV

With verification taking up more and more of the design cycle, is there any hope that verification will keep up with escalating design complexity? Yes, according to panelists at the DVCon conference Thursday Feb. 25. From the discussion, I distilled three basic approaches to improving verification productivity:

  • Raise the level of abstraction for verification and design
  • Apply more intelligence throughout the flow, at every level of abstraction
  • Educate new engineers for real-world design and verification challenges

Verification consultant Brian Bailey, panel moderator, started the discussion on a hopeful note. "We've muddled through a 16X increase in design complexity since 2004, and we're not in verification hell," he said. "We're obviously doing an awful lot right." But how, he asked, will we survive another six years and another 16X increase in design complexity?

1. Raise the level of abstraction for verification and design

Perhaps the most obvious way to improve verification productivity is to move to a higher level of abstraction. This means less code, fewer bugs, easier reuse, and faster simulations. Indeed, as I reported in an earlier blog, Bailey spoke about the advantages of a SystemC transaction-level modeling (TLM) based flow earlier at DVCon.

Panelist Ran Avinun, marketing group director for system design and verification at Cadence, noted that the transition from gate level to RTL began 15 years ago. "We see the same thing happening right now with SystemC," he said. Moving up in abstraction, Avinun noted, makes it possible to separate functionality from constraints and leverage high-level synthesis.



DVCon panelists included (left to right) Brian Bailey, Ran Avinun, Janick Bergeron, Shawn McCloud, J.L. Gray, and Rajeev Ranjan.


"I'm calling for the death of state-based design," said Janick Bergeron, fellow at Synopsys. "That term includes RTL, and C level synthesis that's barely above RTL." Don't start with states, he said - start with the application, build a corresponding virtual platform, and then bring in synthesis and equivalence checking.

Shawn McCloud, director of high-level synthesis at Mentor Graphics, said that a customer survey showed that verification is the number one reason that people move to high-level synthesis. Moving to a high level not only speeds verification, he noted, but makes it easier to find tricky corner-case bugs.

2. Apply more intelligence throughout the flow, at every level of abstraction

This second point is perhaps more subtle, but is no less important. We can move to a TLM-based flow, but that doesn't mean that RTL and gate-level design will disappear. What's needed, Avinun said, is a "unified verification environment that we can use throughout the flow."

This flow, Avinun said, has three components. One is metric-driven verification guided by an executable verification plan and coverage metrics. Another is the use of verification IP, which he said is "as important, or in many cases more important, than [design] IP." A third is scalable performance throughout the verification process. This is where acceleration and emulation become important.

Rajeev Ranjan, CTO at Jasper Design Automation, noted that formal technology can offer improvements during all phases of the verification flow. In particular, he noted, formal tools can allow a "designer pre-verification" without having to generate a testbench.

3. Educate new engineers for real-world design and verification challenges

A point that was made in a Feb. 24 DVCon panel, and reported in my previous blog, is that universities are doing a poor job of training engineers for the real world of IC design and verification. University graduates need a lot of additional training before they're really useful on design and verification projects, and as a result, are often not hired in today's economy.

J.L. Gray, verification consultant at Verilab, moderated the Feb. 24 panel. As a panelist on the Feb. 25 panel, he noted that "the thing I've realized about the advanced verification techniques we need to move forward is that a very large majority of engineers don't have the skills to take full advantage of these techniques."

"The lack of educated people for design and verification is a big challenge," Ranjan concurred. He talked about graduating from U.C. Berkeley in 1997, and noticing that fewer students and professors were involved in IC design and verification.

 "If training is one of the biggest issues, we've got to fix the educational system," Bailey said. That's a tall order. As I wrote last year, the Cadence Academic Network is one attempt to bring real-world relevance into university education. The time has come for an industry-wide discussion of this issue.


Richard Goering


Photo by Joe Hupcey III


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