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DVCon Panel: Why Verification Engineers Are “Sleepless”

Comments(0)Filed under: Industry Insights, DVCon, OVM, verification, IC Design, VMM

I view a panel as successful when I leave the room knowing more than when I came in. Such was the case at the "What keeps you up at night" panel at DVCon Feb. 24, which offered some interesting, provocative, and in several cases surprising perspectives about challenges and solutions in IC design and verification.

Moderator J.L. Gray, verification consultant at Verilab and author of the Cool Verification blog, said the purpose of the panel was to "let people purge, get things off their chests, and have a good discussion to see what kinds of solutions we can come up with." While previous DVCon "Industry Leaders" panels included EDA CEOs or representatives, this year's panel was very different. Participants were:

  • Steven Gary, vice president of professional services at Numetrics Management Systems, a provider of enterprise software tools for IC companies.
  • John Goodenough, worldwide director of design technology at ARM Ltd.
  • Sheela Pillia, senior manager of process, circuit and technologies at AMD.
  • Jim Crocker, vice president of engineering at design services firm Paradigm Works.
  • Victor Melamed, director of engineering at digital media device provider Ambarella.

Following are some of the conclusions I found most interesting.

 


        The "What keeps you up at night" panel included John Goodenough, Victor Melamed, Sheela Pillia,
        Steven Gary, and Jim Crocker (left to right).

 

Analog models come too late, or are just plain wrong

Pillia noted that her group works with mixed-signal blocks with small amounts of digital content. Verification starts with the digital part, but the analog model comes too late. "We are trying to come up with a solution to get an architectural model up front," she said. She also noted that Verilog-AMS is too slow, and that AMD uses a "homegrown" simulation tool that requires a lot of hand-holding.

"When I ask an analog designer to give me a model so I can start verifying, they give me something that is similar but not exactly the same as what they're designing," said Melamed. "My struggle is to convince them that what they give me has to reflect what they're doing."

Flows are more important than methodologies or standards

"Asking about methodology is the wrong question," Goodenough said. "Asking about workflow is the right question, because that's what impacts cost and schedule. There is no end to clever languages. It's more about how you use them in the workflow." He noted, however, that "some languages allow us to be more productive, and some allow easier SoC integration."

People are more important than anything...but training is lacking

Tommy Kelly, CEO of Verilab, spoke from the audience to say that a quality verification team is the key to reaching time-to-market. "I would much rather have a mediocre tool flow and great engineers than a great tool flow and mediocre engineers," he said.

This comment touched off a discussion about the lack of training for new verification engineers, and the failure of universities to prepare new engineers for the real world. "I see a lot of resumes from young engineers coming from school," said Crocker. "There is no adequate software training for people going into this [verification] business."

"Verification is a mix of hardware and software," Melamed said. "New college grads who know a lot about software and a little about hardware do okay. Those who know a lot about hardware and have only rudimentary ideas about software don't do very well."

(Note: Last year I blogged about the Cadence Academic Network, which was set up to help universities train new engineers for real-world occupations).

There can be a "negative benefit" from IP reuse

If silicon IP is not easy to integrate and reuse, it can actually hurt more than it helps, according to Gary. "When the reusable design data falls below 50 percent, the benefit in terms of effort savings is almost zero," he said. "At lower levels, it costs more to try and reuse IP than to build from scratch."

Open source IP is not the answer

An audience member asked if open-source IP will help engineers sleep a little better. Apparently not. "There is no free lunch," Goodenough said. He noted that the software community is large enough to support and maintain open source, but the IC design community is much, much smaller.

"Okay, so you get some open-source VIP and run it in simulation," Melamed said. "When it core dumps, who do you call?"

85 percent of projects are missing schedules

Numetrics helps IC design companies optimize staffing and productivity, and it's a challenge. "We try to keep design cycles short," Gary said. "The reality is that 85 percent of the projects out there are missing their schedules, and unfortunately they're off by 10 to 150 percent. Quantifying tasks is a critical issue."

The $50 question: one vendor or two?

Before the panel, moderator J.L. Gray put out a request for questions and offered a $50 prize for the best question. It was: "Is what keeps you up at night the fact that you went to bed with only one vendor, or more than one vendor?"

If you stick with one vendor, Melamed said, you miss the "flexibility and opportunity" of having two. But having to deal with two or more vendors causes a lot of pain. He then expressed the hope that OVM and VMM will combine into one methodology. As I noted in a recent blog, that is one goal that's now within reach.

 

Richard Goering

 

Photo by Joe Hupcey III

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