In spite
of rumors about the decline of the e verification language, it's not
only still alive but is thriving and growing, according to Mitch Weaver,
corporate vice president for front-end verification at Cadence. In this
pre-DVCon interview, he answers questions about Cadence and industry support
for the e language and the Specman/e verification environment, as
provided by Incisive Specman Elite and Incisive Enterprise Simulator XL.
Q:
Mitch, there have been some rumors that Cadence is not investing in Specman or
the e language any more. What's the
reality?
A: It
always makes me upset to hear any absolutely false rumor or perception
regarding the future of e! First, let me say that Specman/e
is a great business for Cadence. Almost all of our top customers
are using the technology because of its ongoing effectiveness to handle
the giga-gate designs they are developing today. Even with all the
SystemVerilog pressure over the past five years, they have chosen to stick with
e.
They've evaluated all the alternatives and found that Specman/e
excels in speed, ease of use, coding efficiency, scalability, and verification
throughput.
Specman/e
license usage has more than tripled since the Cadence merger with Verisity. The
IntelliGen constraint solver technology was developed after the Verisity
acquisition. Specman continues to successfully provide e support for other
simulators. Of course, we also provide full native e support in our own Incisive Enterprise Simulator XL.
Cadence is thus continuing its investment in the development, integration, and
methodology of e, both in terms of our own products and the vibrant e
ecosystem.
If you
monitor user groups such as Team Specman and Yahoo! Specman, you can see that many customers and partners
are successfully using e and that it is widely acknowledged
as the "best" testbench language available. So, I would like to emphasize that
Cadence has not taken the focus off Specman or e at all. We continue to
enhance this technology and we have a full commitment to our customers to
support them going forward. Bottom line: cutting back on Specman/e
would be like cutting our own throat.
Q: How has Cadence integrated
Specman/e into its functional
verification offerings?
A: Since
the Verisity acquisition, we've been on a serious investment binge around the
unification of Verisity technologies inside our product offerings, particularly
the Incisive Enterprise Simulator. We just did a big release called Incisive
9.2, and its mission was to complete that unification. We had already
integrated the Verisity engine, but this new release goes further by allowing
multi-language verification capabilities.
What this
means is that verification IP [VIP] from anywhere can mix in any fashion and
form. You can have e on top of SystemVerilog and SystemVerilog on top of e,
in any kind of mix and any level of hierarchy you want. We now have a single
verification platform with a single debugger, a single trace generation
capability, and a common assertion capability across all design and
verification languages. INCISIV 9.2 is the complete unification of all
verification technologies around multiple languages.
Q. How is Cadence working to move
the e language forward?
A: Cadence
is aggressively increasing its investments in e language related
products, research, education, technical donations to IEEE 1647, and developers
programs. Specman/e technology is one of the pillars of our
advanced innovation program. Our focus areas include increasing verification
throughput, extending metric driven verification to all non-RTL domains, and
increasing automation.
Q. Verisity used to have a very good
partnership program. However, we don't hear much talk these days from other vendors
about supporting e. Is the ecosystem
still intact?
A: The
ecosystem is still very healthy. Many of our partners have strong verification
IP, services, and training businesses around e. For example, over 43
service providers worldwide and over 250 experts support e. VIP providers include Cold
Spring Engineering, eInfochips, Globetech, and Paradigm Works. AMIQ
offers the DVT development environment. Doulos is among several companies
offering e language education.
One of the
key partners that Verisity had was Novas for debugging. Novas used to strongly
promote the nBench solution for e. As you may know, the partnership
with Novas made sense for Verisity but after the Cadence merger, we integrated
the Specman/e technology into our SimVision product. We believe our
integration of Specman/e is much tighter and more seamless
today than it was in the past with Novas
Q. Isn't
e support expensive and costly to
maintain?
A: The elegance of the Cadence multi-language approach is
that we can support the breadth of the IEEE design and verification languages
by finding novel ways to share resources inside our R&D organization.
Specman/e technology is very strategic to the overall Cadence
verification business.
Some of the key reasons for our ongoing support are that e
is widely acknowledged as the "best" testbench technology available, it is a
mature and proven language for verification of the world's largest chips, and
Specman has a 96 percent track record of first-time silicon success. Many
large, important customers are starting new projects with e. Our own verification
IP depends on e to implement its core functionality.
Q. In that case, can you help us
understand how e fits into the
overall multi-language OVM/UVM campaign?
A: We view OVM
[Open Verification Methodology] as an over-arching technology that is not
language specific. We believe that the key to future SoC design productivity is
the ability to maintain a team's expertise in one language, while being able to
integrate IP that may be implemented in different languages.
OVM e
is the next generation of the Verisity eRM [e Reuse Methodology], which was
the first methodology that provided a framework for verification IP reuse. OVM
is fully backward compatible with eRM, but it also provides some new
capabilities that are especially suited to address the verification challenges
of SoC verification. e users have created the largest
base of methodology-compliant verification IP, and SystemVerilog and SystemC
users can access it via the OVM multi-language capability. This represents a
huge productivity gain because the e VIP is well proven, and
integrating it reduces verification costs regardless of your primary
verification language choice. Of course, if your choice is e, this integration is
even easier.
Q. What is the relationship between
Metric Driven Verification (MDV) and the e
language?
A:
Customers that have the most difficult verification challenges tend to be using
e,
and most of them utilize our metric driven verification solution. Just like the progression from eRM to OVM and
now UVM, the MDV methodology originated and was prototyped with e. It continues today to be the most complete,
stable, and effective solution for implementing highly automated verification
environments. We like the fact that e
is mature, which gives us the ability to implement a full featured MDV solution
for our customers, and have that be risk free from a technology perspective.
Q. I understand that e is IEEE Standard 1647-2008. Is there any current activity in the IEEE 1647
group?
A: Yes. e
was accepted as IEEE standard 1647 in March 2006, and then the spec was revised
in May 2008. The IEEE standards committee is working on a new release of the
standard this year: IEEE 1647-2010. The
working group is on track for an update in the third quarter.
Q. Since e is an
IEEE standard, will Synopsys and Mentor
support it?
A:
Well, they certainly should, since no one can claim to support all
IEEE-standard design and verification languages without supporting 1647!
Customers should not hesitate to ask vendors about their plans to support IEEE
1647.
Q. How do customers considering a
move to more advanced verification view e versus SystemVerilog?
A: Many
of the largest Cadence customers are using Specman/e today for SoC
verification. They have been very successful using the e-based
solutions and plan to continue using it. This year at DVCon, multiple papers are being presented that highlight Specman
performance as well as how Specman/e technology can be used for
mixed-signal verification.
Users
moving from Verilog or VHDL testbenches to more modern verification
environments face a choice between e and SystemVerilog. Of
course we support both languages equally well and are happy with whatever they
choose, but we do make an effort to educate them on the unique advantages that
only e offers.
Q. Speaking of those unique advantages, Specman uses aspect oriented
programming (AOP) while SystemVerilog and SystemC use object oriented
programming (OOP). What's the advantage of AOP?
A: Both AOP
and OOP share the concepts of objects, and enable the users to organize their
code around those objects. AOP can be thought of as a superset of OOP, in the
sense that users generally have to apply OOP concepts first to successfully
apply AOP. But an AOP language such as e allows the user to extend objects
in the environment from within different modules without creating new types.
AOP is a "building-block" superset of OOP for rapid environment construction,
easy reuse, and unlimited scalability. The important point is that AOP makes it
possible to extend an existing program, such as a verification environment,
without modifying the core environment itself.
For
verification engineers, AOP makes it easy to write and run efficient tests, and
to reuse verification environments from block to system and from one project to
another. AOP thus makes e a much more productive
verification language.
Q: What can you say about the
performance of the e language?
A: e
is a high-performance language, on par with C for common procedural code. e
also has a built-in interpreter that makes it possible to load incremental code
on top of a compiled environment, or to debug code without recompiling. Many
past rumors about slow e performance were due to the fact
that people compared e interpreted code to a compiled
version of other solutions. In all the cases we looked at, e proved to be the
fastest language with a real apples-to-apples comparison.
Q. What are the plans for the
Specman/e technology in 2010 and beyond?
A: We
have very detailed roadmaps for Specman and e for 2010 and
beyond. At a high level, we are investing in Specman simulation performance,
debug performance, multi-language integration enhancements, VIP enhancements,
coverage and generation with IntelliGen, and other areas as well.
Q. Is Cadence planning on hosting
more public Specman/e oriented events in 2010?
A: Yes, we
are planning on continuing hosting worldwide "ClubT" events this year. We are
planning the dates now and will roll out the schedule soon. Please join the
Team Specman user group to get the latest details on the ClubT events, and read
Team Specman Cadence community blogs.
Richard
Goering