Embedded software development and hardware/software integration have become primary bottlenecks for system-on-chip (SoC) projects. Still, most EDA tools remain exclusively focused on hardware design, while software development tools have no understanding of hardware. A collaborative solution developed by IBM and Cadence, called the Enterprise Verification Management Solution (EVMS), takes a new direction by providing an automated environment for parallel hardware/software development.
Sold by IBM, EVMS unites hardware and software verification with tools from IBM Rational, IBM Tivoli, and the Cadence Incisive Enterprise platform, along with services from IBM and Cadence. I think EVMS represents the “next generation” of EDA for two reasons:
It extends EDA technology into hardware/software co-verification and embedded software development, providing benefits such as metric-driven verification to software engineers.
- It’s not only aimed at SoC designers and programmers, but also at project managers and corporate executives, and is thus a true “enterprise level” solution.
EVMS aims to bring SoC hardware and software verification together in a comprehensive, automated environment. It includes such capabilities as requirements development and traceability, software lifecycle management, verification planning, workload management, and test development and execution. Further details are included in a feature article on the Cadence web site as well as a description at the IBM Rational EVMS web site.
I mentioned in a previous blog that embedded software development has become the biggest part of SoC development costs at 65 nm and below. Meanwhile, we’ve all heard the statistic about verification taking up 60 to 70 percent of IC design costs. Software verification is even more problematic than hardware verification, since it’s an ad-hoc methodology that lacks such features as verification planning and metric-driven verification.
In most IC design companies, hardware and software design are totally separate disciplines, but not at IBM. EVMS is based on IBM’s hardware/software co-development methodology for SoCs, said Steve Berry, business development executive at IBM. “We’ve been doing [co-development] at IBM for years and the time-to-market and cost benefits are dramatic,” he said. How dramatic? In the IBM Power7 processor design program, Berry said, verification costs at IBM are substantially below the oft-quoted 60 to 70 percent.
EVMS users could potentially run both hardware and software verification from a single verification plan, and bring metric-driven feedback into the Cadence Incisive Enterprise Manager, said Michael Munsey, director of enterprise solutions marketing at Cadence. While hardware and software simulation and debugging run separately, the results could all come together in a “dashboard” customized for a project manager or engineering manager.
By leveraging such technologies as metric-driven verification, EVMS can help bring some rigor and formality to today’s ad-hoc software verification process. It can also help both hardware and software teams understand hardware/software interactions. In addition to bringing a comprehensive methodology to SoC design, EVMS just might point the way to a new generation of advanced, collaborative SoC design solutions.