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DesignCon Panel: “Total” IP Solutions Fuel SoC Integration

Comments(3)Filed under: Industry Insights, SoC, verification, IP, Atrenta, Arasan Chip Systems, DesignCon, Virage Logic

Panelists at DesignCon Feb. 3 agreed that just shipping RTL code for silicon IP is far from sufficient. But what comprises a “total” IP solution for SoC integration? That’s a little more complicated, and it fueled a good discussion with panelists from Arasan Chip Systems, Atrenta, Virage Logic, and Cadence.

I found this discussion particularly interesting because not enough attention has been paid to the challenges of integrating IP onto an SoC. The EDA industry has primarily focused on the creation of IP. When you start to think about what it takes to provide IP that is ready for integration, the list can get pretty long.

“In order to provide a smooth IP integration flow,” said panel chair Ram Gopalan, senior director of corporate marketing at Arasan, “IP providers need to go beyond just providing the RTL IP.” A “total” IP requirement starts with architectural modeling and includes verification IP (VIP), software drivers and stacks, and hardware platforms for development and validation, he said.

Panelists then filled in some details, making the following points:

There are four dimensions to a total IP solution

Prakash Kamath, vice president of engineering at Arasan, said that a total IP solution includes these aspects:

  • Verification IP – bus functional models, test suites, monitors, checkers
  • Services – customization and consulting
  • Platforms – hardware development kits, hardware validation platforms, protocol analyzers
  • Software – firmware, drivers, software stacks

He also said that IP must be optimized for area and performance, and customizable to fit the user’s SoC environment, “with no gaskets or wrappers.”

Software is a critical part of the offering

SoC developers have little time to write software, and are increasingly requesting firmware and drivers along with IP cores, Kamath noted. Atul Garg, who’s in charge of the software component of IP solutions at Arasan, added more details. He talked about the importance of partitioning hardware and software, a task that needs to be performed by the IP provider. If there are components that are likely to change as standards evolve, it may be best to put those in software.

Beyond that, Garg said, the IP provider should make sure partitioning is optimal for selected operating systems, such as Linux, Windows or VxWorks. The IP should be pre-validated under different operating systems. “All of our software components should be portable to any OS,” he said.

Build in quality from the beginning

Satish Soman, chief solutions architect at Atrenta, talked about different “care abouts” as the IP design process progresses. In the initial phases of RTL design, getting the syntax correct is a major concern, while in later phases people worry more about sematic correctness and conformance to the spec. Near RTL completion and handoff, power and testability become key concerns. “Quality needs to be built in during IP development,” he said. “It cannot be at handoff and cannot be an afterthought.”

Different teams have different needs

In large companies, different organizations have different IP needs, said Raghavan Menon, vice president of engineering at Virage Logic. For example:

  • The Central IP team needs a single source (or small number of sources) for IP, uniform quality standards, a close partnership with access to R&D, and IP provided for every process node that’s in use.
  • The SoC Team needs IP blocks that work together, and provide many different “views” for different phases of the design.
  • The System Team needs support for debugging and tuning, reference board designs, software stacks, and emulation for software development.

Meeting the IP/SoC verification challenge

“You need to make sure each IP component is validated thoroughly before you get it,” said Bill Billowitch, marketing director at Cadence. But how? The first requirement is the metric-driven verification flow advocated by Cadence, where you start out with an executable verification plan and then track progress through coverage metrics.

A second challenge is protocol compliance. This typically requires protocol expertise and takes a lot of time. To ease the challenge, Cadence provides its Compliance Management System with all Cadence verification IP. This software provides built-in protocol expertise, along with test scenarios you can use to validate compliance with standards.

Takeaway

Reliance on third-party IP is increasing, and SoC integration challenges are rising. Externally-produced IP needs to be “integration ready.” That means IP providers need to build in quality, validate both hardware and software IP, and provide all the deliverables needed to quickly integrate the IP into a thoroughly verified SoC.

Richard Goering

Comments(3)

By Gary Dare on February 7, 2010
Thanks for being there and taking notes, Richard!  Say, did the Atrenta representative touch on how they make use of IP-XACT to import and utilize IP in their tool, based on the meta-data in those XML files that accompany IP?

And not to put you on the spot but also, vis a vis Cadence? ... since it was an active member of the SPIRIT working groups (schema, verification, ESL, etc.).  :)


By Richard Goering on February 8, 2010
Gary -- I don't recall that IP-XACT came up in the discussion (at least, it's not in my notes). It probably should have. It's part of the solution -- but it's not the entire solution.

By Sameer Patel on February 10, 2010
Atrenta's 1Team®-Genesis solution indeed supports IP-XACT to import IP and leverages the accompanying meta-data for SoC/subsystem assembly as well as for Register memory map generation.
In fact, 1Team-Genesis provides a completely integrated design environment that enables automatic assembly of IP-based subsystems and SoCs, generation of fabric subsystems and software interface management.  It is fully interoperable with other design environments through industry standard formats such as IP-XACT, Verilog and VHDL.

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