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Analog Simulation – Looking Beyond “Wall Clock” Time

Comments(0)Filed under: Industry Insights, Virtuoso, PLL, Analog Simulation, Acellerated Parallel Simulator

clock2 The primary way that people describe or categorize analog simulators is in terms of raw performance – what one might call “wall clock” time. That’s a short-sighted view. The real issue is verification productivity, and that’s a much broader – and more interesting – question that leads us to reconsider the way in which analog verification should be done.

Certainly simulation speed is important. Whether you’re a digital or analog designer, simulation is never fast enough. A common bottleneck on the analog side, for instance, is closed-loop simulations of PLLs. Anyone who claims to speed that up will attract some attention.

As a result, numerous vendors, including recent startups, have emerged with various claims about “fast” analog simulation. Some are offering parallelized versions of Spice on multi-core workstations or GPU platforms. Others are touting various flavors of “Fast Spice,” which trades off accuracy for a boost in performance – and may require a fair amount of tuning to reach the right tradeoff.

Performance claims misleading

But raw performance claims are misleading, notes John Pierce, director of circuit simulation and verification marketing at Cadence. The actual performance of a simulator is not only customer-dependent, but heavily design-dependent. As an example, he noted that the Cadence Virtuoso Accelerated Parallel Simulator running on 4 CPUs could be as much as 50X the speed of single-CPU Spice for a very large circuit, but could be 2X, 5X or 10X the speed of Spice for a small circuit.

As of today, much of the analog verification process is not automated at all. Consider what takes place in PLL verification. After simulating the basic building blocks, designers typically tabulate the block parameters into system models that can be anything from an Excel spreadsheet to a sophisticated MATLAB model. Designers then apply some functions, perhaps written in C or MATLAB; obtain system performance specs for the PLL; and evaluate which corners they really need to simulate. That’s a manual task that could potentially be automated by EDA software.

Thus, to evaluate verification productivity, we have to look at the entire verification process from end to end. The question is not how fast a simulation runs, but how long it takes to get a chip out the door, or prepare a pre-verified IP block for SoC integration. Verification productivity ultimately determines how many designs a team can complete in a given period of time.

Automating analog verification

To really boost verification productivity, John believes that analog simulation should strive for the kind of automation now available to digital designers. Digital verification now provides such technologies as executable verification planning, metric-driven verification, assertions, constrained-random test generation, and coverage. Not all of these capabilities apply to the analog world, but automated results checking would be a desirable feature to add.

Cadence analog simulators today let users set up valid modes of operation for a given device. In effect, this lets designers write an “assertion” to ensure, for example, that voltage does not go below or exceed a certain level in a particular mode of operation. A future step could bring that capability up to block design.

Ultimately, John said, the analog world should follow the digital world in adopting separate verification teams. This will allow analog verification methodologies to develop and mature, and bring expertise and rigor into the analog verification process. But it requires a change in thinking about the roles of analog design and verification.

Now, isn’t this a more interesting discussion than talking about “wall clock” time for a PLL simulation?

Richard Goering


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