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Should IC Designers Worry About Temperature?

Comments(0)Filed under: Industry Insights, Encounter, SoC, digital implementation, Allegro, temperature, Ansys

Three years ago I wrote an EE Times article about the growing importance of thermal gradients and thermal analysis at 90 nm and below. That article turned out to be ahead of its time. Today, thermal issues are not among the top few designer concerns at mainstream process nodes. But indications are that thermal analysis will get a lot “hotter” with the move to advanced process nodes, and will be crucial for stacked-die configurations.

According to Pete McCrorie, director of implementation product marketing at Cadence, there are several concerns with respect to IC temperature. One has to do simply with the impact of an elevated temperature. A hotter chip may require more expensive packaging. Further, as temperature increases, leakage increases exponentially – and leakage is a huge concern at 45 nm and below. Finally, a hotter chip is more prone to electromigration, and may thus have reliability problems.

On-die variations

Of more concern to many designers is the prospect of on-die temperature variations, or gradients, across a die. These variations could be as much as 10°C to 20°C in a well-designed chip. Changing the temperature affects the operating conditions of individual components, and may therefore change chip timing or power consumption.

Today, Pete noted, IC designers typically run multi-corner simulations that include worst-case temperature values, but each temperature corner represents a constant chip temperature. The corners don’t take on-die gradients into account. Designers are thus effectively adding margins to their designs to avoid thermal-related problems. Margins work, but they often result in overly conservative designs, with a sacrifice in performance and/or area.

The biggest audience for thermal analysis today, Pete said, is among companies doing stacked-die designs. In this case it’s critical, because a die that is sandwiched between other dies doesn’t get as much cooling and will have more trouble dissipating heat. Further, thermal gradients must now be managed across an entire stack of closely coupled dies rather than a single die.

Digital IC designers are fortunate in one way – thermal analysis can leverage average power consumption to predict thermal gradients. Cadence Encounter Thermal Analysis, for example, is an option to the Encounter Digital Implementation System that uses distributed power numbers to provide thermal maps that display temperature gradients.

Analog challenge

Thermal analysis is a lot harder on the analog side. According to Randy Fish, product marketing director at Cadence, analog designers often measure real silicon using on-chip thermal sensors or lab-based measurements. Sometimes custom designers can get good thermal estimates from floorplanning. A paper from CDNLive! Silicon Valley 2007 notes the importance of analog thermal analysis and discusses several third-party tools.

Thermal issues are a growing concern for analog designers, Randy said. With voltages dropping, SoCs are mixing high current drive with sensitive analog circuits, and temperature gradients can cause device mismatch. High temperature also has a detrimental impact on device behavior and device noise. Also, many analog signal lines at fine geometries are susceptible to electromigration, which is worsened at high temperatures.

Thermal analysis has long been part of package and printed circuit board design. Today Cadence partners with Ansys, a Cadence Connections partner, for thermal analysis integrated into Cadence Allegro PCB, package, and system-in-package (SiP) products. There’s also an interchange between IC and package design. While the Encounter platform provides a thermal die model for package analysis, the Allegro Package Designer sends back a thermal package model for IC analysis.

So who should be concerned about thermal issues? Anyone who plans to work at 45 nm and below, or use sensitive analog circuitry, or is considering a stacked-die implementation, needs to be aware of the impacts of thermal gradients. For a growing number of design teams, the costs of designing conservatively enough to avoid any possible thermal problems will outweigh the costs of running thermal analysis.


Richard Goering

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