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A Visit To Cadence Research Labs, Part 2

Comments(0)Filed under: Industry Insights, C-to-Silicon Complier, Incisive, Cadence Research Labs, verifier

As noted in part one of this blog series, the Cadence Research Laboratories in Berkeley, California is a unique EDA research organization that has contributed to a number of products and technologies in IC and systems design. What really makes the lab work, however, is its people. My previous blog included an interview with Andreas Kuehlmann, lab director. This posting includes three short video interviews with researchers at the lab.

The first video features Ken McMillan, Cadence fellow and a veteran of the lab since 1994. As noted in a previous blog, Ken invented symbolic model checking as a graduate student. This is a technology that enabled commercial formal property checking tools such as Cadence Incisive Enterprise Verifier (IEV). Ken continued his research in formal verification at the Cadence Research Labs. In this interview, he talks about his background, his research interests, and what he thinks is unique about the lab.

 


The second video includes Joel Phillips, a research scientist at Cadence Research Labs. With a strong background in applied mathematics, Joel has been at the lab for the past 12 years and has researched circuit simulation, timing analysis, interconnect modeling, power modeling, and other topics. He talks about his interests and background in this video clip.

 


Yoshi Watanabe, senior architect at Cadence Research Labs, is researching a timely topic – system-level design. He has been with Cadence since 1997 and has worked on system-level design methodologies, models, and tools, including the Cadence C-to-Silicon Compiler. In this video clip, he talks about his research interests and about hot topics in system-level design research.

 


Thanks for Ken, Joel and Yoshi for these interviews and for their years of research on behalf of Cadence and the EDA industry.

Richard Goering

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