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Q&A: Michał Siwiński Sees Major Shift in Product Design and Verification

Comments(0)Filed under: Industry Insights, chip estimate, verification, IP, C-to-Silicon, Design, Functional Verification, Logic Design, System Design and verification, digital implmentation, ECO management, power-aware

MichalThe rising costs of product development are causing fundamental changes in the design and verification flows, according to Michał Siwiński, group director of front-end product management at Cadence. In this interview he discusses customer challenges and Cadence strategies in such areas as hardware/software co-development, logic design, functional verification, mixed-signal, low-power, and system-on-chip (SoC) realization.

Q: Michal, what does your job function include?

A: I’m accountable for front-end product management including strategy, roadmaps, marketing, and partnerships. In this capacity I’m working very closely with executive management, the corporate strategy team, customers, sales, and R&D to help move the company forward.

The simplest definition of front-end includes anything and everything from concept down to the netlist view of the design, at the point where hand-off to the back-end takes place in our customers’ flows for implementation. The front-end includes all of our offerings related to the hardware-software development process, logic design, and functional verification.

Q: What are the biggest customer challenges?

A: Customers are experiencing a fundamental development crisis. The brute force approach of just adding more resources and compute cycles is not scaling. The unrelenting complexity explosion is not contained to the chip, but is in fact compounded by the inclusion of embedded software that is part of nearly every deliverable that our customers ship to their customers. The current economic realities and market pressures are further exacerbating this challenge, creating a major inflection point.

Let’s think of the numbers for a second. The embedded software for a typical SoC takes up approximately half of the customer expenditure today, and most of that goes into personnel as opposed to automation. The same largely holds true for verification, which makes up over 60 percent of the SoC development costs. Then you throw implementation into the mix where customers are suffering from tail-end iterations, and you can see exactly why we clearly are at crossroads within the industry. Putting it all together, these factors account for the vast majority of project costs -- which have to be automated and contained before they get out of control and become completely unmanageable, effectively stifling innovation.

Q: How are customers addressing the cost and complexity explosion?

To survive and grow, customers are taking risks and moving beyond the classical methodologies that used to work in the nineties and last decade. Making that shift, and making it work, is a critical undertaking, as failure is not an option. Obviously, cost over-runs aren’t too popular, nor is missing the market window.

This is where we as EDA and Cadence come in -- we have the technology, drive and know how to provide the expertise needed to deliver an effective evolution of the development process, which includes smart automation, and deep partnership-style execution to ensure success.

Q: What strategies is Cadence emphasizing in the front end?

A: First and foremost I see the foundation of our strategy being about customer success. While it might sound like a cliché, it’s how we approach business, with deep partnerships being at the core of how we define our vision, direction, and priorities.

In context of development, our emphasis in the front-end, as part of overall Cadence strategy, has been three-fold -- enabling profitability, predictability, and productivity.

Helping with our customers’ bottom line, enabling them to be more profitable, comes first. One way to enable this is by raising the level of abstraction, driving the evolution from register-transfer level [RTL] to transaction-level modeling [TLM] with technologies such as Cadence C-to-Silicon Compiler linked into the design and verification flows. The resulting full TLM-to-GDS flow automation is then complemented by earlier software-hardware verification closure capabilities to streamline project costs and ensure timeline accuracy. These benefits are exactly what our customers have been craving, and we’re seeing unparalleled demand for these sorts of development process automation.

Schedule predictability is next, enabled via early design tradeoffs and metric-driven enterprise verification. The objective to help customers move from traditionally brute force low-tech iterative approaches to a more effective and measurable process, allowing predictable project schedule execution at a lower correlated NRE cost.

Engineering productivity is last but certainly not least. Higher engineering efficiency is enabled via automation and offerings in chip planning and SoC integration, verification reuse leveraging the OVM [Open Verification Methodology] and off-the-shelf verification IP, physically-aware global synthesis for design optimization, ECO management, and power-awareness across the entire integrated flow, to name a few.

Q: Cadence is heavily promoting metric-driven verification. How’s the adoption?

A: With economic forces causing a constant tug-of-war in this extremely competitive market, customers are trying to be data and metric driven in order to be much more effective. This concept extends directly to how they approach SoC verification, as opposed to relying on the traditional brute force approaches. We see the overall proliferation of our OVM-enabled metric-driven verification increasing by at least 3X in the past year alone, to the point where most of the top 50 customers have already used these techniques on several projects. Moreover, those customers are actively expanding the number of internal deployments, as well as the breadth of the underlying metric-driven technology to include everything from formal to emulation.

Q: Accellera just voted to create the Universal Verification Methodology – what does that mean for the OVM?

A: Yes, during the holidays Accellera had a crucial vote for the new Universal Verification Methodology (UVM) standard, making the Open Verification Methodology (OVM) its base.

This is fantastic news for the industry and for OVM. When the OVM was first created by Cadence and Mentor, with links to multi-language support and Synopsys’ VMM added in over time, the aim was to enable a unified means to specifically help our customers scale verification. The UVM, with the OVM as its base, makes this dream ever more real, providing a standards path built upon a proven methodology with a very large user and provider ecosystem. This is just great.

Q: Clearly most SoCs are mixed-signal these days, and require low-power. What is being done in the front-end to help customers with realization of such SoCs?

A: Both low-power and mixed-signal are now part of the mainstream for almost all SoCs at 65nm and below, with Cadence as an established and proven leader in both.

To help customers innovate and maintain profitability, we’re extending the automation capabilities of our mixed-signal SoC integration, verification, and implementation offerings, alleviating challenges related to some of the error-prone and effort-intensive manual steps in the process. The associated risk to overall project cost and timeline need to be mitigated, and that continues to be a focus for Cadence.

When it comes to low-power, given that over 80 percent of power budget is decided prior to logic designers synthesizing RTL, we continue to extend early prediction, analysis, and estimation extending into the system level, while also providing a complete power-aware TLM-to-GDS flow along with power verification, validation, and test.

Q: How is Cadence supporting SoC integration?

A: Since new IP and logic make up a minority of the typical SoC design, obviously customers are doing more reuse, where effective integration is essential. Cadence has been providing IP for a while, and has continued expanding the Verification IP portfolio.

Part of the IP selection and overall SoC realization is the ability to do an early set of what-if cost and architectural analysis along with a first-level raw assembly and high-level floorplan. These are things we already provide through our Cadence Chip Planning technology, and are the entry point to our TLM-to-GDS flow, supported directly by our design and implementation technologies, which have been architected for both fast integration and complexity presented by giga-hertz, giga-gates designs.

Q: Beyond these technology areas, what are customers most concerned about?

A: Customers want to be sure that they can reduce not only their costs, but their overall risk. These concerns are driving a different set of opportunities and dynamics in the market. Cadence is involved in many deep partnerships with customers, and as such is poised to take a good hard look at the problems they’re facing. To that degree we are putting a lot more time into working directly with customers on strategy and execution at the executive level, project level, and engineering level -- moving from the classical notion of being simply a vendor to one of being a trusted partner. While many people say those words, few mean it. We live it, and that is how we get our customers to be wildly successful, driving growth in the electronics industry.

Richard Goering and Michał Siwiński


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