The worst recession of modern times may be over, but the changes it is leaving in its wake will persist. For surviving semiconductor and systems companies, a new top priority has emerged – controlling and reducing both design costs (implementation and verification) and chip costs (such as die size and packaging). The challenge is particularly acute at advanced process nodes, where system-on-chip (SoC) development costs threaten to top $100 million. My forecast is that cost management will play a key role in the electronics industry in 2010, and that the EDA industry will need to help customers get development costs under control.
It’s kind of a good news/bad news situation for the EDA industry. The bad news is that customers will continue to carefully watch spending on everything, including EDA tools. The good news is that the EDA industry can greatly reduce design costs and chip costs, and will obtain good value for its products if it provides the right capabilities.
Here’s what customers will need to do to reduce costs – and how EDA can help:
Accurately predict costs up front
In September I wrote a blog posting about a panel discussion at which Ron Collett, CEO of Numetrics, talked about how SoC development costs are usually significantly underestimated. In many cases, this invalidates the business case for going with an SoC in the first place. Predicting costs early in the design is crucial, but difficult. Chip planning tools that can provide early cost estimates based on die size, power, and packaging, such as the Cadence InCyte Chip Estimator, will become increasingly valuable this year.
Reuse existing IP wherever possible
IP integration and verification in complex SoCs remains a tough challenge, especially for mixed-signal SoCs. While the EDA industry has focused on IP design, it’s time to realize that integration is important as well, and that SoC integration requires a distinctive set of methodologies and tools. Meanwhile, forward-looking IP providers will supply IP that is easier to verify and integrate.
Move to higher levels of abstraction
By greatly increasing designer productivity and reducing resource requirements, moving to higher levels of abstraction will reduce SoC development costs. But a non-standard, high-level tool with no connection to implementation is of little value. In 2010 SystemC transaction-level modeling (TLM), combined with high-level synthesis, will come into broader use for IP creation, integration and verification.
Use verification effectively and efficiently
In these times, no one can afford expensive mistakes – but most companies can’t afford a massive and lengthy verification effort, either. Any approach that can find bugs quickly, resolve them, and reach coverage goals will be welcome in 2010. Metric-driven verification with functional coverage will find more adherents, the use of formal verification will increase, and static checks available in tools like the Cadence Encounter Conformal products will help avoid some long simulation runs. More attention will be paid to mixed-signal SoC verification and to verification of low-power ICs.
Reduce software development costs
Analysts say that software is the biggest development cost at advanced process nodes (see my previous blog on this topic). In 2010 the EDA industry will become more involved with this challenge through technologies such as virtual platforms, hardware/software co-verification, and emulation. Metric-driven verification techniques will be brought into the software world through tools such as Cadence Incisive Software Extensions.
There’s an old adage – “fast, good, cheap -- pick any two.” In 2010, the EDA industry will need to focus on helping customers optimize time-to-market, quality, and cost without compromises. In so doing, we will be seen as a strategic asset rather than an added cost burden.