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Preparing The Next Generation Of IC Designers

Comments(8)Filed under: Industry Insights, IC Design, CDNLive!, VLSI Design, Cadence Academic Network

While many universities offer classes in VLSI design, it is very difficult for universities to turn out graduates who can go right to work as chip designers. As a result, there’s a looming shortage of engineers in key areas such as RF, mixed-signal and verification. How can this gap between academia and industry be bridged?

An academic network set up by Cadence in Europe in 2007 demonstrates one way of helping universities prepare students for the real world. Further perspectives came from a recent panel discussion at CDN Live! India, entitled “What does it really take for students to be industry ready?”

Cadence Academic Network
The Cadence Academic Network was the idea of Patrick Haspel, who was a lecturer at the University of Mannheim (Germany) in VLSI design and computer architectures prior to joining Cadence in 2005. Patrick noticed that it’s very difficult for universities to stay on the leading edge of chip design technology. He initially joined Cadence as a technical advisor to the sales team for Infineon, but having come up with the idea for a network, he was asked to implement it – and since then, managing it has become a full-time activity.

Patrick told me that the network today includes about 30 actively participating universities, located all across Europe including Russia. Recently, he said, there’s been some interest in expanding the network to India. Some European universities have been identified as “lead” universities in particular areas. For example, the University of Heidelberg is the lead university for high-level verification, the Technical University of Ilmenau focuses on RF design, and the Albert Ludwigs University of Freiburg concentrates on mixed-signal design.

Why is there a need for the network? “If you talk to any semiconductor or systems company, they will tell you they need to train new hires for 6 to 18 months before they are really productive in a project,” Patrick said. “Very few universities do a good enough education so that a new graduate can immediately start working productively in a project.”

The goal of the network, Patrick said, is “to lower the barrier for universities to stay on the leading edge of any microelectronic topic.” The network provides far more than just access to Cadence or partner tools. It also provides methodology help, and to this end, Patrick makes extensive use of Cadence methodology kits. Patrick becomes, in a sense, an “account manager” for the member universities, and just like an account manager for a customer, he helps universities solve problems, manage projects, and gain access to leading-edge tools, libraries and IP.

The Cadence Academic Network is behind the academic track at the CDN Live! EMEA conference. This track, launched in 2008, gives universities a chance to present their work to both academic peers and industry attendees. CDN Live! EMEA is set for May 4-6, 2010, in Munich, Germany.

“Industry Ready” Panel Discussion
A detailed report of the CDN Live! India panel discussion appeared in a recent blog posting by technology journalist Pradeep Chakraborty. Panelists cited various ways for students to be “industry ready” in IC design, including the following points:

  • Come into the industry with an attitude of collaboration
  • Develop deep technical skills for jobs that are “an inch wide and a mile deep”
  • Be up to date on current challenges, like low power design and high-speed serial interfaces
  • Be prepared to interact with multi-cultural teams, and learn to communicate well
  • Look for apprenticeship opportunities for on-the-job training

Patrick’s take is that producing “industry ready” graduates requires a new approach to education in which conditions are similar to what students will encounter in the industry. Instead of the classical “lecture and lab” setup, students should have real projects with milestones, team leaders, and project meetings. I think this is an interesting idea. A tapeout that’s due before the final exam will convey a sense of urgency for which graduates need to be well prepared.

Richard Goering


By Pradeep Chakraborty on December 11, 2009
Hello Richard, Many thanks for posting a link to my blog post, Richard. Incidentally, I also covered Lip-Bu Tan's keynote @ CDNLive, India.

By drjay on January 18, 2010
Thanks, Richard, for outlining the Cadence Academic Network efforts! As a senior scientist at Ulm University Germany, which is also a member of the network, I would like to emphasize the benefits of such collaboration.
The pure availability of software is only a minimum requirement to educate students. It would mean nothing, if we were only able to show them how to draw a schematic or synthesize an HDL-code. With the rapidly expanding new techniques like Advanced Parallel Simulation, Ultrasim Full-chip simulator and Analog-mixedsignal / Digital-mixedsignal, it is crutial for us university teachers to stay up to date with the latest simulation- and design- methodologies. The Cadence Academic Network provides us with insight to these new methodologies and we can immedeately teach them to our students. The thorough understanding of the software methodologies is a key to meaningful simulations and working designs.
Feedback from industry partners in the Stuttgart and Munich area tells us  that our graduates are highly welcome and early productive due to their hands-on experience during studies. However, be aware that they are expensive for  the companies, because they immedeately request the latest software updates and tend to check out the most expensive license features ;-))
Cheers, Joachim

By Ana Rusu on January 29, 2010
Thanks for summarizing the Cadence Academic Network initiative, Richard!
Patrick’s idea of building this network was great. As Assoc. Prof. within the RaMSiS Group from Royal Institute of Technology (KTH) Stockholm, Sweden, member of the Cadence Academic Network, I would like to point out two benefits of being member of the network.
Today, when new technologies emerge and advance at a very fast pace, the complexity of the electronic systems increases and the industry needs engineers with broad skills and technology competence. In this context, the micro-/nano- electronic engineering education must prepare the students to fulfill these needs. Cadence Academic Network helps us in this matter. One benefit of being member of the network is the access to the latest information about the design methodologies, tools, new features and troubleshooting, as well as technical support, which is very important for our education and research in the area of RF/analog and mixed-signal design. This is critical for us since we perform multi-mode design, where mixed-signal (RF, analog, digital), multi-level and multi-domain simulation and design are involved, and the methodology and tools become very complex.
We also benefit from the Cadence Academic Network itself. Discussions with teachers from other universities, experts from Cadence and industry were very valuable and showed that our teaching approaches have industrial relevance.

By Ralf Sommer on January 29, 2010
Hi Richard,
I also like to thank you for your analysis of the challenges of an industrial oriented education and how important especially a tight link between university and industry is. Forming exactly that link and connecting universities is the goal of the Cadence Academic Network, thus building a strong bridge between university partners and the leading EDA vendor Cadence.
Prof. Barke, president of the University of Hanover and EDA expert, identified that more than 50% of redesigns were caused by pure design errors mainly due to imperfect use of tools, badly structured, risky design style and lacking knowledge in design methodology, in tool capabilities, as well as in fundamental relationships.   Most of these points have to be addressed in education at the universities; and this exactly shows why we need an academic network – come together, exchange experiences and innovative ideas in chip design and especially discuss design methodology in combination with leading-edge EDA   - that is the direction designers will have to be educated and where new inspirations to solve future design challenges are born!
(Technical University of Ilmenau and Institute for Microelectronic and Mechatronic Systems GmbH)

By Ulrich Bruening on February 1, 2010
The Cadence Academic Network was a great idea of Patrick, which I had the pleasure to educate in chip design and computer architecture. The benefit of this network is manifold. Getting in contact with people working on the same or similar problems in education and research helps a lot. Many helpful connections have been established with the meetings at CDN live and other events. Educating students using the brand new features of tools from Cadence make them very productive staff members in industry and the feed back we got from industry showed that this it an excellent way to improve the quality and applicability of our lectures.

Being able to access Cadence resources and support to fix problems with design flows and learning the methodology from the experts in the training courses is another benefit.

We as a university group highly appreciate that we are recognized as partners in this network and thus we can contribute to the evelution of the community.

We hope the network will continue to grow and provide advantages to all participants.



By Kerstin Eder on February 2, 2010
For us, the Cadence Academic Network adds real value to the microelectronic design and verification teaching here at the University of Bristol. For instance, in my Design Verification course I use the latest version of Specman Elite for labs and coursework. Being familiar with the e language, the latest verification tools and methodologies gives our students a competitive edge when it comes to employment; it simply equips them with the knowledge and skills expected from professional verification engineers. In your words, Richard, this helps prepare the "next generation of *verification engineers*", a new breed as most of my students have a Computer Science background, so they know high-level programming paradigms and write fantastic e code.
The Cadence Academic Network enables me to keep abreast with the latest development in EDA tools and even more importantly the latest methodologies to fully exploit the scope of these tools. In collaboration with Patrick we are currently in the process of setting up a complete lab for students to use the full range of Cadence tools for microelectronic system design and verification during their education at Bristol. Bridging the gap between education and industry is vitally important to meet the recruitment needs of the local microelectronic design industry, and the Cadence Academic Network acts as a true facilitator in this respect.

By Matthias Keller on February 4, 2010
Dear Richard,
For more than seven years, I am involved in teaching and corporate industrial projects at the chair of Microelectronics of the University of Freiburg. In that time, a steadily increasing gap between academia and industry was also observed for several reasons. Before joining the Cadence Academic Network in 2007 as the lead university for mixed-signal designs, teaching our students based on the latest design and simulation methodologies was difficult to achieve. One reason consisted in providing the appropriate software for the huge number of students. Besides, there was no possibility to keep pace with the steadily changing needs of simulation methodologies. The students thus were taught a thorough theoretical background of microelectronics while using freely available software which is not necessarily industrial standard. Only when it came to a diploma thesis, students were taught the use of industrial standard software. This approach was less effective since it had to be performed in parallel to the diploma thesis whereby the student was distracted from the research. Furthermore, the student could only learn the basic functionalities of simulation software while putting emphasis on special topics according to the needs of the thesis. As a result, companies have to train the new hires for at least another six months before they become productive which exactly equals the scenario you described.
Today, after being three years a member of the Cadence Academic Network, much has changed. Based on the active exchange between the members of the lead universities and by means of the excellent support by Dr. Haspel, we are always up-to-date on the latest simulation methodologies; thus keeping pace with them. Thereby, a change in our curriculum became possible. Students now are taught the complete design flow of an integrated circuit in our courses. The benefits of this approach are on hand. Students can focus on the research related to the diploma thesis. Moreover, industrial partners confirmed that we already had narrowed the gap between academia and industry and encouraged us to proceed in this manner. An overwhelming success which became only achievable based on the Cadence Academic Network initiated by Dr. Haspel.
Best regards from Freiburg

By Mladen Berekovic on February 14, 2010
Dear Richard,
I am very happy that you raise the issue of student education and access to tools
and methodologies and reference to the Cadence Academic Network (CAN) as an initiative
to overcome the well-known insufficiencies in this area.
I am teaching a VLSI curriculum at TU Braunschweig, that was setup in close
collaboration with the nearby Intel labs with the specific goal to improve student education
such that the warmup phase for new hires in a company like Intel can be significantly reduced.
The CAN has been a formidable instrument in this challenging endeavour, not only by providing tools
and kits that - for the first time- offer the latest technologies for student education, but also
by providing a support network where you can share knowledge, experiences and methodologies with
others. Without this ecosystem, demanding technologies like e.g. power gating or MPSoC design would be out-of
reach for education. Having the students work with SoA industry tools and environments  
reduces the training phase in the companies dramatically. Indeed we have had good experience
with students doing their master thesis at Intel that were able to work on top-notch
projects in just half a year of time.
I also fully appreciate your comment that we have to do more in the direction of letting the students work in
practical labs in small design teams that work _together_ to solve a larger project, not just individually.
Forcing them to interface with their peers helps raise their sensitivity for team work project management. Our experience
shows that they run into the typical hassles, e.g. communication & coordination problems that limit
the effectiveness of the teams in achieving their overall goals together. For the students this is typically an eye-opening
Having attended the “Industry Ready” Panel Discussion at the last CDNLife! India I was surprised by
the openness awareness of the Indian educational industrial establishment to these very same issues.
This clearly demonstrates to me that these challenges are global and that by connecting in networks like CAN we
can achieve a lot more and educate better engineers in the future.
TU Braunschweig, responsible for Advanced VLSI Design curriculum

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