Home > Community > Blogs > Industry Insights > what is verification ip interoperability
 
Login with a Cadence account.
Not a member yet?
Create a permanent login account to make interactions with Cadence more conveniennt.

Register | Membership benefits
Get email delivery of the Industry Insights blog (individual posts).
 

Email

* Required Fields

Recipients email * (separate multiple addresses with commas)

Your name *

Your email *

Message *

Contact Us

* Required Fields
First Name *

Last Name *

Email *

Company / Institution *

Comments: *

What Is Verification IP Interoperability?

Comments(0)Filed under: Industry Insights, OVM, Verification IP, VIP

Verification IP (VIP) interoperability is widely discussed these days, but is not often clearly defined. Most people think of VIP interoperability in terms of the work that the Accellera VIP technical subcommittee is doing with respect to the Open Verification Methodology (OVM) and Verification Methodology Manual (VMM). That’s important, but the interoperability issue goes well beyond methodology standards.

I recently talked to Mike Stellfox, distinguished engineer at Cadence and a member of the VIP subcommittee, about VIP interoperability. The real issue is reuse, he noted. Since building verification environments is a complex task, it is very helpful to reuse verification assets in the form of VIP that can handle stimulus, checking, coverage, and other tasks. Cadence, for example, offers Incisive VIP for protocols such as AMBA, MIPI, PCI Express, USB, and many others.

Mike identified three kinds of reuse:

  • Horizontal reuse is reuse from one project to another. If you have VIP for the AMBA AXI interface, you’ll want to use it for all projects that use AXI. The VIP needs to be written so it can easily work with testbenches written for different designs.
  • Vertical reuse makes it possible for the same VIP to work with both block-level and system-level testbenches. “A lot of VIP is traditionally written in a way that makes it very difficult to reuse vertically,” Mike noted.
  • Diagonal reuse lets you reuse a testbench across different execution engines. This may include SystemC simulation, RTL simulation, formal property checking, assertion-based verification, and emulation.

Mike noted that OVM, which supports multiple languages including SystemVerilog, SystemC, and e, facilitates horizontal, vertical and diagonal reuse.

There are, however, two commonly used methodologies – OVM and VMM. It’s all IEEE 1800 SystemVerilog, you may ask, so what’s the problem? The answer is that the language does not dictate a methodology. If you have an OVM testbench and a VMM piece of VIP, they probably won’t work well together.

The Accellera VIP subcomittee has a two-step approach to the OVM/VMM interoperability problem. First, the committee announced the Accellera VIP “Recommended Practices” interoperablity guide in September. If you follow the instructions in this guide, you’ll be able to link that OVM testbench with the VMM VIP, or vice versa. Further, the guide includes an interoperability library that provides some extensions to the base class OVM and VMM libraries that help ease the connection.

The second step, as Accellera announced in September, is an ongoing effort to develop a common base class library and associated verification methodology to enable VIP reuse, with the goal of achieving IEEE standardization. It is not yet known what form this will take. There are many considerations, including the need to support existing OVM and VMM environments, testbenches coded in both SystemVerilog and e, and models coded in SystemC.

A standardized, common base class library will definitely make VIP interoperability and reuse much easier. But VIP developers will still have to provide interoperability across projects, abstraction levels, and verification engines. VIP purchasers should not only ask about methodology support, but also about horizontal, vertical, and diagonal reuse. Standards just make interoperability possible – they don’t make it real.

Richard Goering

Comments(0)

Leave a Comment


Name
E-mail (will not be published)
Comment
 I have read and agree to the Terms of use and Community Guidelines.
Community Guidelines
The Cadence Design Communities support Cadence users and technologists interacting to exchange ideas, news, technical information, and best practices to solve problems and get the most from Cadence technology. The community is open to everyone, and to provide the most value, we require participants to follow our Community Guidelines that facilitate a quality exchange of ideas and information. By accessing, contributing, using or downloading any materials from the site, you agree to be bound by the full Community Guidelines.