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User Challenges Drive New Generation of PCB Design Tools

Comments(0)Filed under: Industry Insights, PCB Design, Allegro, PCB 16.3

PCB design has been a quiet little corner of the EDA industry that’s typically overshadowed by IC design. But every chip must ultimately go into a package and onto a board, and given the increase in IC complexity and speed, that job can’t be getting any easier. That thought led me to wonder what’s going on in PCB design these days. Faster routing? Better signal integrity tools? Surely something interesting must be happening.

It turns out the real picture is much broader. Customer business challenges are driving new design strategies aimed at miniaturization, bandwidth, shorter design cycles, and energy savings. These demands could result in a significant retooling in PCB and IC package design. There’s more detail in a recent series of whitepapers from the Cadence PCB and IC package group.

The whitepapers, which do not discuss products, describe design challenges and needed solutions as follows:

1. Miniaturization and complexity

Problem: More functionality is being squeezed into smaller and smaller form factors. With advanced process nodes, ICs are growing smaller, but the number of I/Os is increasing. Interactions between ICs, packages and boards have a large impact.

What needs to happen: Interconnect routing that can handle small packages with large numbers of bumps or balls. Embedded devices on inner PCB layers. Substrates that allow high-density interconnect (HDI) and microvias. Support for Rigid-Flex PCB substrates. Support for system-in-package (SiP). IC-package and package-PCB co-design.

2. Faster data throughput

Problem: Everyone wants more bandwidth, and interface standards run at double or triple the speeds of a few years ago. Interconnect between ICs must keep up with multi-gigabit data rates.

What needs to happen: Interoperable I/O models not tied to specific simulators. 3D modeling for package interconnect. Integrated simulators and field solvers. Compliance testing for communications protocols employed in the design.

3. Shorter design cycles

Problem: Time to market pressures demand fast design turnaround times. There are too many iterations during the PCB design process.

What needs to happen: Constraint-driven design flows with rules stated up front. A constraint-driven flow that supports HDI rules. Design authoring that combines schematics with other representations (such as tables for large pin count ICs). Design for reuse. FPGA/PCB co-design and pin assignment. Support for team design.

4. Environmental concerns

Problem: Compliance with directives like RoHS and WEEE is needed for global marketing. Consumers are increasingly concerned about energy consumption and carbon footprint.

What needs to happen: Access to compliant parts and materials. Tracking compliance through bill-of-materials. Leveraging product lifecycle management (PLM) software.

These issues will be explored more thoroughly at a Virtual Conference to be held Wednesday, Dec. 2. The conference will discuss the recent Allegro and OrCAD 16.3 releases, which address many of the points cited above. It will also feature speakers from DownStream Technologies, Motorola, Artwork Conversion, Xilinx, Schlumberger, Dassault Systems, and other customer and partner companies. Clive “Max” Maxfield will give what is sure to be an entertaining keynote entitled, “Electronics Miniaturization Through The Ages (From Antiquity to the 25th Century).” Max offered a preview in a recent blog.

Further information and free registration for the virtual conference is available here.

Richard Goering


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