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Guest Blog: Characterizing Process Variability At 32 nm And Below

Comments(0)Filed under: Industry Insights, IBM, Stratosphere Solutions, CMOS, 32nm

Jim_Bordelon1

Process characterization becomes much more complex as feature sizes shrink. In this guest blog Jim Bordelon, president and CTO of Stratosphere Solutions, describes requirements and methodologies for modeling variability at 32 nm and below.

Peering under the hood of a 32 nm process early in its lifecycle provides a wealth of information about the challenges awaiting designers and EDA tool providers alike. A recent 32 nm test chip project conducted with Cadence, IBM and Stratosphere Solutions included a suite of characterization structures designed to measure transistor variability. As discussed in a previous blog, the variety of “contexts” that a transistor experiences within the community of other transistors in the design can strongly influence both the performance and yield of the product circuit. How big and how close your neighbor is matters.

Cadence and Stratosphere have developed modeling techniques to capture and incorporate variability into the design flow. Stratosphere provides specialized test chips and modeling tools that supply fundamental variability information that the Cadence Encounter toolset uses to accurately assess the statistical timing and power characteristics of a product. Stratosphere’s Strato-Pro testchip produces volumes of raw data that our Ozone modeling tool crunches to generate models of variability that span many different transistor contexts. This task introduces new requirements for both silicon characterization and data modeling.

On the characterization front, many transistor contexts must be distilled into suitable test structure DUTs (devices under test) and replicated to yield a statistically significant set of test data. In principle, this is no different from the conventional device characterization that all fabs have done. Today, though, the large variety of structures and sample sizes required for a leading CMOS process dictate a much higher density of test structures than what is economically achievable with conventional testchips, and require a faster method of test as well.

Once upon a time, fabs relied on testchip data from multiple dice on multiple wafers from multiple lots to build a statistical picture of the process. The statistics of device variability at 32 nm must be modeled within die so that the systematic and random components of variability can be teased apart, modeled, and applied appropriately by the EDA toolset. Random variations impact circuit performance and yield differently than do systematic variations.

High density, array-based, characterization circuits like StratoPro combine test devices with active addressing circuitry designed to be robust to process variations. The result is somewhat like a memory array, but with cells containing various sets of replicated DUTs that are testable in an analog fashion (such as sweeping a MOSFET gate voltage and measuring a drain current) and useable on early process mask sets. The array serves the dual purpose of enabling many more types of DUTs, design rule experiments, and context experiments, as well as allowing DUTs to be easily replicated without chewing up more valuable mask area.

Distributions of many device parameters over a wide range of device variations (both sizes and contexts) are obtained from measurements of one array. Considering that multiple arrays can be placed on a test chip, multi-project wafer die, or even a scribe line, a large amount of data is produced that gives a detailed statistical picture across multiple spatial domains associated with an array, die, reticle, and wafer. The hierarchy of data enables the extraction of systematic variations which exist at the die, reticle, and wafer levels, as well as the intrinsic random variations. The systematic variations are important for ascertaining deterministic relationships between device properties and device size, context, and spatial location.

As an example of many DUT contexts studied, a poly line that closely abuts the end of a 32nm MOSFET poly gate was seen to significantly reduce the random variability of the threshold voltage and the systematic variation of threshold voltage with gate width. Ring oscillator data clearly indicated a spatial systematic variation across a wafer of NAND gate delay as high as 28% of the mean value. Stratosphere’s Ozone tool separates spatial systematic variability from the underlying random variability of all types of measured data, and also reports correlation between variations of different device and circuit parameters. Empirical variability models created by Ozone enhance the accuracy of statistical EDA engines further upstream in the design flow.

Together, high density test vehicles and statistical data modeling tools constitute the front end of the emerging statistical EDA infrastructure. Stratosphere’s tools have been run at multiple fabs and proven from 65 nm down to 32 nm. Incorporating the silicon-accurate variability models produced by these tools within the Encounter tool suite for simulating timing, power, and standard cell performance results in a design capability for 32nm and below that offers true optimization of performance and parametric yield.

Jim Bordelon

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