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User Interview: Formal Analysis Speeds IP Connectivity Verification

Comments(0)Filed under: Industry Insights, IFV, Xilinx, CDNLive!, RTLL Compiler, Formalmal, Incisive Formal Verifier

The biggest challenge with verification is “always the schedule,” according to Chaitanya Kosaraju, senior design engineer at Xilinx. Thus, anything that can cut verification time without compromising coverage presents a huge advantage. At the recent CDNLive! Silicon Valley, Kosaraju showed how formal analysis reduced verification times from 3 ½ months to 1 month for a multiplexed pad interface block.

Kosaraju gave a paper entitled “Time-Saving Formal Analysis Approach for Multiple IP Connectivity Verification” at CDNLive! In it, he discussed the challenges of using a conventional simulation testbench approach for verifying a multiplexed pad interface, given the large number of possible input combinations. He showed how he used the Cadence Incisive Formal Verifier (IFV) to verify the entire block, with no need to generate test stimulus, set up functional coverage points, or write assertions from scratch.

In an interview after his presentation, Kosaraju further discussed his experiences with IFV. In the video clip below he tells how and why he uses formal analysis, how he saved verification time on his pad interface block, and how he developed assertions.


If video fails to launch click here.

The pad interface block was Kosaraju’s first experience with IFV. There wasn’t much of a learning curve, he said, given that the IFV Connectivity Package automates the generation of assertions. Kosaraju observed that Xilinx found 16 bugs in a one-month period in the pad interface block, including bad RTL mappings, discrepancies in the spec, and documentation errors.

His advice for teams considering formal analysis? “Building the testbench environment takes so much time,” Kosaraju said. “If management wants to see some results, you can employ IFV and do some basic checks before your testbench is up and running.” He also advised engineers to “look at areas of the design where formal will probably fit, and where you have to use your testbench for verification. I think they both go hand in hand.”

Richard Goering

Call for papers! The CDNLive! EMEA conference will be held May 4-6, 2010 in Munich, Germany, and abstracts for proposed paper submissions are due December 11, 2009. An academic track at the conference, developed by the Cadence Academic Network, is seeking paper submissions as well. The academic track provides a forum for university researchers to present their work to both academic peers and industry attendees.


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