Home > Community > Blogs > Industry Insights > user interview how to estimate power early
 
Login with a Cadence account.
Not a member yet?
Create a permanent login account to make interactions with Cadence more conveniennt.

Register | Membership benefits
Get email delivery of the Industry Insights blog (individual posts).
 

Email

* Required Fields

Recipients email * (separate multiple addresses with commas)

Your name *

Your email *

Message *

Contact Us

* Required Fields
First Name *

Last Name *

Email *

Company / Institution *

Comments: *

User Interview: How To Estimate Power Early

Comments(0)Filed under: Industry Insights, Incyte, Encounter, CDNLive! Silcon Valley, RTLL Compiler, Power, IDT

Early power estimation makes it much easier to manage IC power, according to Camille Kokozaki, director of design automation services at Integrated Device Technology (IDT). At the recent CDNLive! Silicon Valley, he presented a case study of architectural power estimation with a 65nm system-on-chip with 250K logic cells and a maximum frequency of 400 MHz.

Kokozaki described a flow that uses five steps:

  • “Back of envelope” estimations in spreadsheet provide assumptions about voltage, dynamic power factor, leakage power factor, design for test overhead, and other factors.
  • Power estimation from InCyte Chip Estimator uses a provided model library. InCyte estimates dynamic power sensitivity versus activity.
  • Cadence Encounter RTL Compiler provides estimation from early synthesis run.
  • More accurate estimation based on full synthesis netlist.
  • Power calculation from post-layout netlist.

Accuracy increases with each successive step, but the higher levels of abstraction provide a greater ability to influence power.

In an interview following his presentation, Kokozaki discussed his approach to power estimation further. In the attached video clip, he discusses the importance of power analysis at an architectural level, and talks about his use of spreadsheets, InCyte, and pre-synthesis and post-synthesis power estimations.

 


If video fails to launch click here.

For the chip described in the CDNLive! case study, IDT employed clock gating. Kokozaki said IDT also uses more advanced power management techniques where appropriate.

Kokozaki had a warning about the use of activity levels in power estimates. “Be very careful about activity and what it means,” he said. “There are cases where a 10 percent activity for a particular mode can consume even more power than a 15 percent activity rate on a different mode in the same design. You have to know what you’re putting in there. I also advise people to not go overboard and use a much higher activity rate than what they end up seeing.”

Richard Goering

Comments(0)

Leave a Comment


Name
E-mail (will not be published)
Comment
 I have read and agree to the Terms of use and Community Guidelines.
Community Guidelines
The Cadence Design Communities support Cadence users and technologists interacting to exchange ideas, news, technical information, and best practices to solve problems and get the most from Cadence technology. The community is open to everyone, and to provide the most value, we require participants to follow our Community Guidelines that facilitate a quality exchange of ideas and information. By accessing, contributing, using or downloading any materials from the site, you agree to be bound by the full Community Guidelines.