Early power estimation makes it much easier to manage IC power, according to Camille Kokozaki, director of design automation services at Integrated Device Technology (IDT). At the recent CDNLive! Silicon Valley, he presented a case study of architectural power estimation with a 65nm system-on-chip with 250K logic cells and a maximum frequency of 400 MHz.
Kokozaki described a flow that uses five steps:
“Back of envelope” estimations in spreadsheet provide assumptions about voltage, dynamic power factor, leakage power factor, design for test overhead, and other factors.
- Power estimation from InCyte Chip Estimator uses a provided model library. InCyte estimates dynamic power sensitivity versus activity.
- Cadence Encounter RTL Compiler provides estimation from early synthesis run.
- More accurate estimation based on full synthesis netlist.
- Power calculation from post-layout netlist.
Accuracy increases with each successive step, but the higher levels of abstraction provide a greater ability to influence power.
In an interview following his presentation, Kokozaki discussed his approach to power estimation further. In the attached video clip, he discusses the importance of power analysis at an architectural level, and talks about his use of spreadsheets, InCyte, and pre-synthesis and post-synthesis power estimations.
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For the chip described in the CDNLive! case study, IDT employed clock gating. Kokozaki said IDT also uses more advanced power management techniques where appropriate.
Kokozaki had a warning about the use of activity levels in power estimates. “Be very careful about activity and what it means,” he said. “There are cases where a 10 percent activity for a particular mode can consume even more power than a 15 percent activity rate on a different mode in the same design. You have to know what you’re putting in there. I also advise people to not go overboard and use a much higher activity rate than what they end up seeing.”