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Why Stress Gives Designers Headaches at 45 nm and Below

Comments(0)Filed under: Industry Insights, 45nm, transistor stress, Litho analyzer, advanaced node, digital implmentation, encountern

Transistor stress may become the dominant source of systematic variation at 45 nm and below, yet there’s been surprisingly little discussion about this issue. Today, stress-induced variability is primarily a concern for design teams who are pushing the envelope in terms of advanced nodes or performance. Tomorrow, it may impact most ASIC and SoC designers.

I became aware of this issue during the Advanced Node panel at the Cadence Ecosystem booth at the Design Automation Conference. Panelists noted that stress is a major cause of systematic variability at 32/28 nm, that regular Spice models don’t comprehend stress properly, and that placement needs to be optimized to control stress-induced variability. To get more information about stress, I talked to Nishath Verghese, engineering group director for electrical DFM at Cadence.

Unlike emotional stress, transistor stress in deep submicron ICs is intentionally induced for the most part, and is generally a good thing. By placing tensile or compressive stress onto NMOS or PMOS devices, Nishath noted, you change the lattice structure inside a transistor channel, allowing electron mobility to be higher. This boosts performance. Also, by changing the velocity at which transistors saturate, stress can allow higher performance at high voltages.

There are various ways of inducing stress, and the actual methods vary from one foundry process to another. One way is to “strain” silicon by introducing another layer on top of silicon, such as silicon germanium (SiGe). Another is to introduce a “capping” layer, such as a silicon nitride layer over a polysilicon gate. Dual stress liner (DSL) is a technology in which both NMOS and PMOS devices are stressed, while single stress liner (SSL) stresses only one of these device types.

Note that I said above that stress is “intentionally induced for the most part.” Stress is unintentionally induced by shallow trench isolation (STI), which uses oxide to isolate transistors and results in silicon dioxide abutting against silicon. “Even if somebody says they don’t use strain and don’t need to model stress, that is not correct,” Nishath said.

At 65 nm, Nishath noted, designers cared only about the distance between a transistor gate and the nearest STI edge. At 45 nm and below, what becomes important is the width of the STI channel. Knowing that requires a knowledge of where the next transistor is. We have thus introduced a proximity effect, meaning that one transistor is influenced by the placement of its neighbors. If the next transistor is placed too close or too far away, “my stress is changed and the performance of my device has changed,” Nishath said.

The main impact of stress is timing variability, and at 45 nm stress can cause variability by as much as 15 percent, Nishath said. At 32 nm the variability will probably be higher. This makes it hard to close timing. “If you want to account for this you either need to margin excessively, which means your timing closure gets longer, or you need to actually calculate the impact,” Nishath said.

So what to do? Foundries are now modeling stress effects by creating extensions to the classic BSIM model that take proximity information as an input. The standard digital design flow, however, assumes that every standard cell is independent of all others. The Cadence Encounter Digital Implementation System, in combination with Cadence Litho Electrical Analyzer (LEA), can derate standard cells during timing closure based on their contextual influences. Further, LEA can “score” cells based on characteristics of neighboring cells, and EDI runs a post-placement optimization that moves cells around to mitigate stress-induced variability.

The next question is how to help analog designers. Their problem, Nishath said, is that because of proximity effects, post-layout simulations no longer match the schematic. Analog designers need to capture stress variability effects before post-layout simulation. Cadence is working on solutions in this area.

Awareness may be the biggest hurdle. “I think people have kind of swept [stress] under the rug at 45 nm,” Nishath said. “People close to fabs have a very good understanding of it, but people going to foundries are probably less aware of it.” It sounds like transistor stress will be a much more frequently discussed issue in the near future.

Richard Goering


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