Home > Community > Blogs > Industry Insights > cdn live silicon valley a video invitation from cadence cmo john bruggeman
Login with a Cadence account.
Not a member yet?
Create a permanent login account to make interactions with Cadence more convenient.

Register | Membership benefits
Get email delivery of the Industry Insights blog (individual posts).


* Required Fields

Recipients email * (separate multiple addresses with commas)

Your name *

Your email *

Message *

Contact Us

* Required Fields
First Name *

Last Name *

Email *

Company / Institution *

Comments: *

CDN Live! Silicon Valley -- A Video Invitation From Cadence CMO John Bruggeman

Comments(0)Filed under: Industry Insights, Digital implemntation, Custom IC, RF Design, Functional Verification, Logic Design, CDNLive! Silcon Valley, PCB Design, IC Packaging and System-in-Package, System Design and verification

CDNLive! Silicon Valley, the largest of the CDNLive! Cadence user conferences, will be open for worldwide participation in 2009. This year’s conference is a webinar-based event that allows on-line participation as well as on-site attendance at Cadence’s San Jose, California headquarters. CDNLive! Silicon Valley runs two weeks – Oct. 5-9 and Oct. 12-16 – with on-site attendance available throughout the first week.

Why attend CDNLive! Silicon Valley? In the attached video clip, John Bruggeman, Cadence Chief Marketing Officer, explains how the conference can benefit you and your company.

If video fails to launch click here.

This year’s conference includes a technical program of over 60 webinars given by Cadence representatives, partners, and customers. Both on-site and remote attendees can discover best practices for boosting design productivity, get a closer look at Cadence products and solutions, and find out how peers are differentiating their designs and staying ahead of the competition. Those who attend live in San Jose can also network with their peers and exchange ideas in person, as well as attend hands-on workshops in custom design, functional verification, and digital implementation.

The first week, Oct. 5-9, offers tracks including Custom IC, PCB Design, IC Packaging and System-in-Package, RF Design, Logic Design, System Design and Verification, Functional Verification, and Digital Implementation. This week includes presentations from customers such as AMD, Cisco, Hitachi, IDT, Marvell, Micron, National Semiconductor, and Texas Instruments, as well as partners including ARM, CoWare, and Virtutech.

The second week, Oct. 12-16, is available on-line, although several presentations Monday and Tuesday can also be attended on site. Tracks include Custom IC, Digital Implementation, Functional Verification, Manufacturing Signoff, PCB Design, Logic Design, and System Design and Verification. This week includes presentations from Avago, Broadcom, Chelsio Communications, Freescale, Galazar, Hewlett-Packard, KMET Electronics, LSI, IBM, National Semiconductor, PMC-Sierra, RF Silicon, and Texas Instruments.

A detailed agenda is available on line. Registration is open until 5 pm Pacific time Wednesday, Sept. 30.

Richard Goering


Leave a Comment

E-mail (will not be published)
 I have read and agree to the Terms of use and Community Guidelines.
Community Guidelines
The Cadence Design Communities support Cadence users and technologists interacting to exchange ideas, news, technical information, and best practices to solve problems and get the most from Cadence technology. The community is open to everyone, and to provide the most value, we require participants to follow our Community Guidelines that facilitate a quality exchange of ideas and information. By accessing, contributing, using or downloading any materials from the site, you agree to be bound by the full Community Guidelines.