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User Interview: Running Full Chip Mixed-Signal Simulations

Comments(0)Filed under: Industry Insights, SoC, Mixed-Signal, SiRF, GPS, AMS

Running full-chip, mixed-signal simulations with sufficient accuracy and speed is a huge challenge for system-on-chip (SoC) designers. But engineers at SiRF, a provider of GPS chipsets and subsystems, have been able to do so, according to Marcelo Silva, verification engineer. In an interview at the Design Automation Conference, Silva talked about SiRF’s use of Verilog-AMS, real value modeling, Spice, and fast Spice for analog/mixed-signal simulation.

Prior to the interview, Silva spoke at a panel discussion on mixed-signal design and verification at the Cadence Ecosystem booth. Here, he talked about the challenge of running simulations that combine large amounts of digital circuitry running at slow clock speeds with analog/RF IP running at perhaps 3 GHz. Maintaining sufficient accuracy on the analog side while keeping run-times reasonable is a huge challenge, he said. Silva discussed an approach that uses verification planning, a single testbench driven by digital verification engineers, Verilog-AMS at the block and chip level, and real value modeling with the Verilog-AMS wreal construct.

In the interview, Silva noted that SiRF designs its own analog blocks, and thus has both analog and digital design systems and engineers. The company uses the Cadence Virtuoso system for custom design, Virtuoso AMS Designer for mixed/signal verification, and the Incisive Plan-to-Closure methodology for digital verification.

In the attached video clip, Silva talks about how SiRF models analog blocks, and discusses how the company uses Verilog-AMS, full Spice with Virtuoso Spectre, fast Spice with Virtuoso UltraSim, and wreal modeling in order to verify its mixed-signal SoCs.


If video fails to launch click here.

Still, there’s room for progress. Silva noted he’d like to see better handling of voltage scaling in mixed-signal simulation. He would also like to see an analog/mixed-signal version of SystemVerilog, analogous to Verilog-AMS. That would help with randomization and coverage in mixed-signal test generation, he noted.

Silva also spoke to a deeper challenge at the panel – communications between design teams. “Usually the analog and digital guys never talk to one another,” he said. “In our flow, it has to be integrated.”

Richard Goering

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