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Building an SOI IP/EDA Infrastructure

Comments(0)Filed under: Industry Insights, SOI, Green Electronics, CMOS, silicon-on-insulator

My last blog on silicon-on-insulator looked at the low-power benefits of SOI. But performance and power gains are meaningless if you can’t design and manufacture a chip. Fortunately, the needed infrastructure to support SOI design is falling into place.

As the SOI Consortium noted in a Design Automation Conference presentation, the SOI semiconductor ecosystem is expanding. Foundry support is available from Chartered, GlobalFoundries, Freescale, IBM, and UMC. SOI-ready libraries and silicon IP, memory IP, EDA tools and methodologies, and design services are all available from various providers. As the presentation notes, one tool that supports SOI implementation is the Cadence Encounter Digital Implementation System.

ARM, which has been a strong supporter of SOI, offers a physical IP SOI library portfolio. It includes a standard cell library, I/O library, memories, and tools. At the recent Design Automation Conference, Cadence announced validation of 45 nm IBM SOI ASIC libraries from ARM using the Encounter Digital Implementation System. “This should accelerate the IP infrastructure build-out,” commented Jeff Wolf, director of membership development at the SOI Consortium.

According to Rahul Deokar, product marketing director at Cadence, SOI does not significantly change the IC design flow. The main challenge for EDA tools is to correctly model the “history effect” that occurs because the threshold voltage of a transistor may depend on its previous states. This occurs because of the “floating body” transistor effect.

Chin-Chi Teng, vice president of research and development at Cadence, added that Cadence accurately accounts for the history effect in library characterization and that these models are then seamlessly used during timing/signal integrity (SI) analysis and design optimization. He said that Cadence offers a “two-pass” signal-integrity analysis capability that’s especially useful for SOI. It mostly operates at the cell level, but has the capability to drop down to the transistor level for critical portions of the chip to ensure that no SI violation is missed.

“The Cadence SOI design flow is very pushbutton,” Rahul said. “You just bring in the characterized library, and all of the other steps are the same IC design flow.”

The biggest enabler for SOI, Rahul said, will be the availability of libraries and IP. “I believe the libraries are getting ready,” he said. “IP will be an ongoing process.” While there is “increasing interest for sure” in SOI, he noted, adoption is so far mainly limited to the IBM ecosystem.

As with all new technologies, SOI brings about a chicken-and-egg kind of situation. IP availability is needed to drive adoption, but most third-party IP providers will want to see adoption before moving ahead. I think ARM deserves a lot of credit for jumping in ahead of the curve. Now it’s up to SOI advocates to make a strong enough case for the technology to move it from specialized, high-performance applications into the IC design mainstream.

Richard Goering

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