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Green Electronics – Is SOI The Answer?

Comments(0)Filed under: Industry Insights, SOI, Green Electronics, CMOS, silicon-on-insulator

Silicon-on-insulator (SOI) technology has been used primarily for performance-hungry applications that can justify the additional wafer cost. The SOI Consortium recently launched a “Simply Greener” campaign to promote SOI for power savings. While SOI can substantially reduce power consumption, the amount of power you’d actually save for any given SoC design depends on your application, your goals with respect to power and performance, and the processes being compared.

The SOI Consortium is clearly hoping to bring SOI into the IC design “mainstream” with its Simply Greener message. Meanwhile, an emerging foundry and IP infrastructure is making SOI available to fabless companies. But comparing SOI power and performance to what you’d get with bulk CMOS is complicated. Few design teams can afford to spin silicon on two different process technologies and measure the results.

SOI provides an insulating oxide layer that lowers junction capacitance, thus resulting in performance gains and/or power savings compared to bulk CMOS. Smaller transistors and reduced supply voltages help as well. In announcing its Simply Greener initiative, the SOI Consortium reported that SOI chips compared to bulk CMOS “can realize energy savings of 30 percent or more when designed with the same feature size at equivalent performance.” If you want to go for more performance, the power savings will be less, but there should be an area savings in any case.

One thing I’ve noticed, however, is that most quoted numbers about SOI power savings don’t provide a breakdown of dynamic versus leakage power. In researching a feature story on SOI for SCDsource in early 2008, I was surprised to find controversy over whether and how much SOI helps reduce leakage. In one comparison of a 65 nm high-voltage threshold (HVT) SOI process versus a bulk CMOS HVT process, total power savings was 16% for SOI, but leakage was 25% higher. However, in this example the apparent goal was increased performance, which improved by 32% over bulk CMOS. When frequency was held the same, SOI leakage was 37% lower.

To get some more detail on the leakage question, I talked to Jeff Wolf, director of membership development at the SOI Consortium. The first thing he noted is that it depends what kind of leakage you’re talking about. Gate leakage is virtually the same for SOI and bulk CMOS, he said, but SOI “dramatically” reduces substrate leakage, due to the buried oxide insulating layer. Source-drain leakage today can be controlled by back biasing. In the future, ultra-thin, fully-depleted SOI (FDSOI) 22 nm technology may come close to eliminating source-drain leakage, as well as offering good variability control. That’s one conclusion of an IEDM 2008 paper on FDSOI given by the LETI research institute.

Another consideration is what SOI is being compared to. These days, as Wolf noted, while low-leakage CMOS processes have become mainstream, we have yet to see a low-leakage optimized SOI foundry process in production. Based on early data, he said, it appears that SOI “G” processes still offer a leakage reduction compared to low-leakage bulk CMOS processes.

Acknowledging that “apples to apples” comparisons are difficult for design teams to make, the SOI Consortium reported an interesting benchmark with the Simply Greener announcement. The benchmark was conducted by ARM Holdings using a 24-stage datapath circuit. When comparing IBM’s 45 nm bulk CMOS high-performance and 45 nm SOI technologies, the SOI implementation resulted in a 25% circuit area reduction, 66% static power leakage reduction, nearly 22% dynamic power reduction, and 5% higher performance.

It would be good to see more examples like this. What would also be interesting is a power and performance comparison between SOI and high-k metal gate (HKMG) technology, since it appears both will be strong at 32 nm and below.

Of course, the cost comparison is another set of numbers that needs to be run, but remember that the additional wafer cost could be offset by reduced area and gains in performance or power savings. Yet another consideration is the availability of a foundry/IP/EDA infrastructure, but I’ll address that in a follow-up blog. Cadence is actively supporting that infrastructure.

Choosing a silicon technology is a complicated and difficult decision to make, and the more data that’s available, the better. SOI certainly won’t be the answer for everyone and it won’t be the only low-power or high-performance option. Still, the day may come when SOI is nothing exotic, but just another technology on the “short list” that most mainstream IC design teams consider.

Richard Goering

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