Mixed-signal verification is a tough challenge, especially when full-chip simulation is needed. But there are solutions, and some of them surfaced at a panel at the Cadence Ecosystem booth at the recent Design Automation Conference. Engineers from SiRF (GPS chipsets), Cambridge Analog Technologies (analog IP), Micron Technology (NAND flash) and the Cadence services group shared their approaches, successes, challenges and advice for an attentive audience.
Marcelo Silva, verification engineer at SiRF, is running full-chip simulations on mixed-signal SoCs with analog and RF components. These simulations, he noted, combine large amounts of digital circuitry running at slow clock speeds with analog IP blocks running as fast as 3 GHz. Keeping accuracy on the analog side while retaining a reasonable run time is a big challenge, he noted.
“To do mixed-signal verification, we try to inherit some good practices from digital verification,” Silva said. SiRF uses a vPlan (verification plan) and a single testbench driven by a digital verification team. The company also makes extensive use of the Verilog-AMS wreal construct, which allows a real value to be assigned to a single-bit wire. This makes it possible to simulate analog behavior at digital simulation speeds – for instance, PLL lock time can be simulated in 20 seconds.
As a provider of high-performance, low-power analog IP, Cambridge Analog Technologies (CAT) faces a different set of demands. Kush Gulati, CAT CEO, noted that the sensitivity of analog circuits requires extreme precision, tight error tolerance, high-quality models, and simulations that are long enough to capture all relevant non-idealities. CAT needs Spice-level accuracy, and uses the Cadence Virtuoso Spectre simulator extensively. For checking functionality, designers use Cadence Virtuoso UltraSim, a fast Spice simulator.
Prashanth Aprameyan, senior verification engineer at Micron Technology, noted that NAND flash combines the challenges of microprocessor design with the challenges of analog design. He said that Micron has a “unified verification methodology for digital and analog,” and employs Verilog, Verilog-A, fast Spice, and Spice. Even with Verilog-A modeling for analog blocks, however, simulation run-times are still a challenge, Aprameyan said. His wish list includes a more robust analog/digital co-simulation capability and a design for yield (DFY) analysis in fast Spice.
Eric Naviasky (left) speaks as panelists Prashanth Aprameyan, Kush Gulati, and
Marcelo Silva (left to right, seated) listen.
Eric Naviasky, chief technologist at Cadence, spoke from his experience managing mixed-signal designs for the Cadence services group. “First of all, planning is number one,” he said. “If you’re not planning, you’re not going to figure out when you’re done, and you’re going to miss things.” Naviasky added that “you need a verification plan early, and you have to strictly follow it every single time. If somebody moves a single wire you have to run the plan again. Otherwise, I guarantee they will have just disconnected something important.”
One prescription for verification success, Naviasky said, is “easy simulations for easy problems, hard simulations later on.” For example, you don’t want to run a three-day simulation and then find out you have a bias problem. It would be much better to run a bias check beforehand. He also noted that a self-checking testbench is the best way to record your specification.
Naviasky’s admonition about planning was picked up by other panelists in concluding remarks. “Everything is about planning,” Silva said. “Apply the right tool to the right test and do good planning.”
“Start off with your design plan, your layout plan, and your verification plan in parallel,” said Aprameyan. “These are three legs of a platform and they have to exist together.”
“Leave plenty of time for verification,” Gulati said. “Be paranoid. And simulate a lot.”