ESL and silicon IP are regarded as two different topics, but in reality they are closely intertwined. This occurs in two significant ways. First, the availability and interoperability of transaction-level modeling (TLM) IP will be a crucial enabler of ESL-based flows. Secondly, IP reuse is perhaps the biggest advantage of such flows. While these statements may appear obvious in retrospective, they do raise several interesting questions.
In a Tech Trends article for the Aug. 25 ChipEstimate.com newsletter, I wrote about two ESL-related events at the recent Design Automation Conference (DAC) at which panelists talked a lot about IP modeling. Specifically, they talked about the availability (or lack thereof) of third-party TLM models, the use of SystemC TLM models in virtual platforms, the need for high-level synthesis of TLM-based IP, the not-fully-solved problem of SystemC model interoperability, and what to do about legacy RTL models in virtual platform environments.
Without interoperable, TLM models of silicon IP, it will be difficult to construct virtual platforms, employ high-level synthesis, or move verification to higher levels of abstraction. This gives rise to the first interesting question – who will develop these models?
I think the answer varies. Many large semiconductor companies will internally develop SystemC TLM models of their own IP. But will commercial IP providers offer TLM models? There are a few solutions – for example, ARM offers Fast Models, which are instruction-accurate models that can run in SystemC TLM 2.0 wrappers.
RTL models, however, will be with us for a long, long time, especially for “commodity” IP. Thus, there will be a need for design and verification environments that can handle a mix of TLM and RTL models. Emulation will be helpful because it can accelerate legacy RTL models to acceptable speeds.
A second interesting question: What is IP model “interoperability,” and are we there yet? At a virtual platform panel at the Design Automation Conference, panelists noted that the Open SystemC Initiative (OSCI) TLM 2.0 standard is a good start, but more is needed. For example, debug interoperability is lacking. Standard model interfaces could allow simulations that span abstraction levels, and “best practices” for model development could be helpful.
If we can answer these questions about model availability and interoperability, then we can build TLM-based flows that allow a new level of IP reuse. That’s because TLM-based IP does not lock one into a given micro-architecture. By employing scripts with a high-level synthesis tool such as Cadence C-to-Silicon Compiler, you can reuse the same IP block in a number of different micro-architectures. But now we are running into another interesting question – how will this reuse capability impact the way IP is provided?
We’re at an inflection point. It is time for silicon IP providers to start thinking about what lies beyond RTL.