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User Interview: What to Expect At 32 nm and Below

Comments(0)Filed under: Industry Insights, advanced node, AMD, Global Foundries, DAC DFM

Norma Rodriguez, senior member of technical staff at AMD, has a good idea of what IC design teams can expect at 32 nm and below. AMD already has a production design for manufacturability (DFM) flow for this process node, and the flow makes use of restricted layout patterns as well as DFM tools.

At the recent Design Automation Conference (DAC), Rodriguez gave a presentation at the Cadence Ecosystem booth about a capability called DRC Plus. It augments standard design-rule checking by using fast 2D pattern matching to identify hotspots, or layout patterns that result in poor printability. Embedding this capability into a router lets designers identify and fix potential 2D yield detractors. AMD, Global Foundries, and Cadence contributed to the project.

Rodriguez was also a panelist at the advanced node panel at the Ecosystem booth, where she talked about restricted design rules (RDRs) and DFM. In a subsequent interview, I asked Rodriguez what problems got worse at 32 nm compared to 45 nm.

“What is new is that all the metals came with a very problematic litho situation, so there were a lot of forbidden pitches we needed to take care of,” she said. Further, dual stress liner (DSL) technology gets more complicated at 32 nm, and it’s difficult to model the correlation between performance and stress until large production volumes are available.

In the attached video clip, Rodriguez talks about how 32 nm is a “middle point” between 45 nm and 22 nm with respect to RDRs, and what “truly restricted” design rules at 22 nm will involve. She also addresses a question about area tradeoffs resulting from RDRs.


If video fails to launch click here.

RDRs may reduce the need to run model-based DFM tools, Rodriquez said, but they won’t eliminate it. Model-based DFM will still be used for verification, but with RDRs, models will be less crucial for design.

Rodriguez noted that there are typically two “DFM insertions” into the design flow – one that retargets designs for mask data preparation, and another that brings in yield recommended rules (YRCs) to improve manufacturability. A better approach for 32 nm, she said, would “combine retargeting and YRC all in one step and do the DFM as you do your construction.” This, combined with regular patterns provided by RDRs, will help create designs that are “very OPC friendly and manufacturing friendly.”

Who on the IC design team needs to be concerned about manufacturability? Is it just the layout people, or also the logic designers? Her short answer: “Everybody.”

Rodriguez’ advice for design teams considering 32 nm is “to not be scared, but to embrace the idea that things are to the point where we need to collaborate together. Design rules the way we used to think of them are not sufficient. That’s a fact of life you have to live with. You have to check for patterns, you have to check for different types of litho rules to do your design, and you have to favor uniformity.”

Richard Goering

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