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Low Power Panel: Looking Back, Looking Forward

Comments(0)Filed under: Industry Insights, ASIC, ARM, DAC, low power, Faraday, Global Unichip

How far have we come with low-power IC design, and where do we need to go from here? Panelists at the Cadence Ecosystem booth at the Design Automation Conference had some compelling answers for both questions Tuesday, July 28. Two panelists were from ASIC design services companies – Faraday Technology and Global Unichip. One was from ARM, and one was from Cadence.

Rather than come up with a blow-by-blow account of who said what, I have come up with two lists derived from panelist commentary – 1) what’s helping now, and 2) what’s needed in the future. Here are some of the things I’d put in either list.

What’s Helping Now

The implementation efficiency of low-power designs has greatly improved at Faraday, said Albert Chen, filed applications and marketing manager. He showed a slide that depicted an increase from around 10K gates/day in 2006 to over 80K gates/day in 2009. One reason is Faraday’s switch to the Common Power Format (CPF).

Albert Li, director of the design development division at Global Unichip, noted that most designs he sees use multiple voltage thresholds. MTCMOS power gating is coming on strong, power shutoff is becoming more widely used, and dynamic voltage and frequency scaling is beginning to appear.

Ashley Stevens, solutions architect at ARM, talked about a power management kit that ARM has developed to help minimize leakage. He discussed a research chip that used this kit along with ARM production libraries and a CPF-based tool flow. Designers were able to infer header switches and retention flops, and to manage in-rush starter current to avoid state corruption. Stevens also discussed ARM’s 40 nm and 50 nm multi-channel libraries, which can result in a 75 percent leakage savings. Area overhead ranges from 5 to 10 percent.

Alex Sgouros, SoC architect for ESL and low power at Cadence, noted that Cadence design services has used a CPF-enabled flow to “tape out hundreds of chips with a 98 percent success rate.” Noting the importance of system-level power estimation, he talked about use of the Cadence InCyte Chip Estimator and Palladium emulator for early power estimations.

Sgouros also talked about dual flops as a “no brainer” low-power design technique, available today, that can result in a 20 to 40 percent savings in the clock tree. “You can use it almost for free in terms of overhead and get significant reductions for power,” he said.

 

LP_panel
Alex Sgouros, Ashley Stevens, Albert Chen, and Albert Li (left to right) discuss
low-power strategies at the Cadence Ecosystem booth.

 

What’s Needed in the Future

Chen noted that most of the potential power savings are at the system level. “We’ve really only addressed everything from the netlist on down,” he said. “The architectural implementation and its impacts have not yet been fully addressed. It’s really the system level we have to concentrate on.”

While measurement accuracy increases as you go down in abstraction, the ability to influence power increases as you go up in abstraction, Sgouros noted. “The architectural tradeoffs and the hardware/software tradeoffs is where you’re going to affect power the most.”

“Among low power challenges, testing is the most important. Testing is the one thing that has not been covered very well,” said Li.

Stevens mentioned several “things I’d like to see the EDA guys solve in the future.” One is the use of formal techniques to determine which critical states need to be retained, so as to minimize overhead required for retention flip-flops. Another is dynamic well biasing for variable bias generation, bias routing, and dynamic bias optimization. A third is to minimize Vdd with fault-tolerant technology, providing, as he said, “a way to reduce voltage until you start introducing errors into the design, and then recover from that process.”

Stevens also talked about silicon-on-insulator (SOI), which is today primarily used to boost performance, as an option that can reduce dynamic power by up to 30 percent at the same clock speed.

Verification of low-power designs remains a problem. One challenge, Chen said, is generating accurate test vectors to test SoCs for power consumption. He also spoke of verifying a low-power chip with over 3,000 corners and noted that a “rule based” approach is needed for such chips.

What stood out for me most was Chen’s comment that “a more holistic approach” is needed to address power concerns. “I think the systems and software guys have to start talking to the hardware designers,” he said. “It doesn’t really do much good to design a very low power chip and then have a regulator sitting right next to it that’s taking up 30 percent of your power.”

Richard Goering

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