Home > Community > Blogs > Industry Insights > user interview how stmicroelectronics uses virtual platforms
Login with a Cadence account.
Not a member yet?
Create a permanent login account to make interactions with Cadence more conveniennt.

Register | Membership benefits
Get email delivery of the Industry Insights blog (individual posts).


* Required Fields

Recipients email * (separate multiple addresses with commas)

Your name *

Your email *

Message *

Contact Us

* Required Fields
First Name *

Last Name *

Email *

Company / Institution *

Comments: *

User Interview: How STMicroelectronics Uses Virtual Platforms

Comments(0)Filed under: Industry Insights, RTL, System C, Virtual platform

STMicroelectronics relies heavily on virtual platforms for pre-silicon software development and hardware/software verification of its consumer products. Some of the responsibility for the development and use of these platforms falls to Laurent Ducousso, IP verification and software development platform manager at ST.

Ducousso appeared on two panels at the recent Design Automation Conference. The first was a virtual platform panel at the Cadence Ecosystem booth, where he noted that ST is on such a short time scale that the company needs to develop hardware and software concurrently. The only way to fulfill this need, and to get a start on early software development, is with virtual platforms, he said. At the panel, Ducousso also spoke about ST’s use of a “hybrid” approach that combines virtual platforms with emulation. This is a valuable capability when more model accuracy is needed, or when only RTL is available for an IP model.

Ducousso also spoke at a lunch panel sponsored by Cadence, Calypto, and Forte. Here, he provided a broad view of how ST uses SystemC transaction-level modeling for architectural exploration, hardware implementation, firmware development, driver development, and functional verification. He also noted a number of “blocking points” for widespread TLM use, including a lack of SystemC profiling and debugging tools.

In the short video clip below, Ducousso talks about how ST uses virtual platforms, what kinds of software can be developed with them, where models come from, and what’s challenging about virtual platform development. In answer to the last question, he notes that virtual platforms are created in the hardware world and then used by software designers, and that a “huge gap” still exists between hardware and software design environments.

If video fails to launch click here.

In this interview, although not on the video clip, I also asked what’s available and what’s most needed in terms of tool support. Ducousso said that automated tools are available to help with assembly and compilation of virtual platforms, but a profiling capability is still needed.

But what I find most intriguing is Ducousso’s mention of a cultural gap between the hardware and software design worlds. It appears that what is needed is not just better tools, but a new level of mutual understanding and cooperation among hardware and software designers.

Richard Goering


Leave a Comment

E-mail (will not be published)
 I have read and agree to the Terms of use and Community Guidelines.
Community Guidelines
The Cadence Design Communities support Cadence users and technologists interacting to exchange ideas, news, technical information, and best practices to solve problems and get the most from Cadence technology. The community is open to everyone, and to provide the most value, we require participants to follow our Community Guidelines that facilitate a quality exchange of ideas and information. By accessing, contributing, using or downloading any materials from the site, you agree to be bound by the full Community Guidelines.