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DAC Report: A Reality Check On SystemC And TLM

Comments(0)Filed under: Industry Insights, DAC, SystemC, RTL, TLM

An optimistic yet realistic appraisal of SystemC and transaction-level modeling (TLM) took place at the Design Automation Conference Tuesday, July 28, as vendors and users talked both about the advantages of this emerging methodology and what must still be done to make it commonplace. The lunch panel was sponsored by Cadence, Calypto, and Forte.

With three vendor panelists and three user panelists, the discussion focused on the issues with hardly any mention of products. Mike “Mac” McNamara, vice president and general manager of the Cadence Systems Software Group, started the presentations with a look at what’s needed to take design to a higher level. His list: 1) a single model that represents behavior for prototyping, verification and implementation; 2) synthesis with high quality of results (QoR); 3) verification that takes advantage of TLM abstraction; and 4) standards including SystemC itself.

Are we ready to move up to SystemC and TLM-driven design? Yes, Mac said, but some things still remain to be done. These include unifying the TLM 1.0 and 2.0 standards, introducing plug-and-play between levels of abstraction, building solid links to virtual platforms, and “earning the trust” of new tools and methodologies. “We are at the turning point,” he said.

Sean Dart, CEO of Forte, put it another way by saying “we are close to reaching critical mass.” He predicted that over the next couple of years, over 50 percent of new designs will start with C-based tools. Tom Sandoval, CEO of Calypto, emphasized the importance of verification across abstraction levels.

Users always provide good reality checks, and moderator Mark Johnstone, chief technologist at Freescale, didn’t disappoint. He noted that there were a lot of objections when Freescale started to introduce SystemC to its designers. One problem: it’s based on C++, “arguably the most complex programming language ever developed.” On the other hand, the advantages are compelling, given the fact that logic per square millimeter has doubled every year since the advent of Moore’s Law.

Laurent Ducousso, engineering director at STMicroelectronics, noted that his company uses SystemC TLMs practically everywhere – for architectural exploration, hardware implementation, firmware, driver development, and functional verification. Motivations include productivity, architectural choice, and better support for software. But he cited a number of “blocking points.” Examples: tools have limitations with respect to design size and clocking, SystemC profiling/debugging capabilities are limited, and SystemC/RTL co-simulation “needs improvement” to better show cause and effect.

Yutetsu Takatsukasa, technical engineer at HD Lab, noted some of the benefits of high-level synthesis. Simulation is 20-500X faster, and there’s high reusability and “less stress” for the engineer, he said. One thing that’s needed now is a standardized synthesizable SystemC subset, he noted.

Jen-Chien Yeh from ITRI, a Taiwanese research institute, brought some impressive data from a recent experiment with high-level synthesis. Not only did his data show a reduced design time from 12 months to four months – it also showed a better quality of results. Specifically, synthesized RTL beat hand-crafted RTL in gate count and power, with the same critical path timing. (Like the other user panelists, Yeh didn’t mention products by name – but he is scheduled to talk at the Cadence Ecosystem booth Thursday about ITRI’s experience with high-level synthesis).

Mark Johnstone, who was recently profiled in an Industry Insights blog, summed things up by noting that SystemC won’t completely replace RTL – no more than RTL has completely replaced custom design. But will designers move to SystemC and TLM as a mainstream design practice? “We have to,” he said. “There is no other solution when you look at the next level of complexity.”

Richard Goering


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