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DAC Report: 8 Design Managers Reveal Top Concerns

Comments(0)Filed under: EDA, Industry Insights, DAC, ESL, DFM, SoC

Put eight opinionated design managers from top semiconductor companies into a room, let them speak and answer questions, and some interesting perspectives will emerge. That was the case at Management Day, sponsored by Cadence, at the Design Automation Conference Tuesday, July 28.

Organized by Yervant Zorian of Virage Logic, Management Day was an all-day affair that mostly consisted of two sessions of detailed presentations. To be brief, they included the following:

  • Rani Borkar, Intel, challenges in microprocessor design
  • Philippe Magarshak, STMicroelectronics, 3D stacking
  • Don Friedberg, LSI Logic, next-generation networking platforms
  • Alan Nakamoto, PMC-Sierra, design management of 5-month SoC
  • Pierre Garnier, Texas Instruments, design challenges in multimedia processors
  • Chrisoph Heer, Infineon, IP development and sourcing decisions
  • Ed Nuckolls, Freescale, EDA challenges in zero-defect culture
  • Albert Li, Global Unichip, tradeoff analysis in SoC designs

What I attended was the third session, which was a concluding panel moderated by veteran EDA editor and blogger Peggy Aycinena. Faced with eight panelists and only one hour, Peggy asked a number of rapid-fire questions and demanded fast answers. Some of those questions were:

What’s the most critical decision you have to make in design?

Three of the eight panelists mentioned power (“meeting power budgets,” “finding right mix of low-power techniques,” and “power/performance tradeoffs”). Other choices: technology node choice, interface between chip and firmware, using existing tools or adopting new ones, IP selection, and scheduling vs. time-to-market.

If you could cite one technology problem, what is it?

Two panelists cited power. Other answers: software, hardware/software partitioning, hardware/software interaction, predictability, SoC integration including RF, modeling accuracy. I find it interesting that three of eight answers involved software.

What are you not getting from EDA vendors that you’d really like to have?

This was an interesting one – nearly all answers here focused on some type of co-design or co-simulation capability. Answers included: analog/digital simulation, matching software drivers to hardware, cross-domain optimization, analog co-simulation, chip/package co-design, integrated design tools, “true” hardware/software co-simulation, and system/package co-design.

Is DFM or DFY a problem for you?

Basically, those working at advanced process nodes said “yes.” Those working at mature process nodes said “no.” Does this mean that DFM is just not that big of a deal for mainstream designers?

Everyone talks about ESL – is anyone actually moving up?

STMicroelectronics clearly is. Most others were not very far along. Several said tools are “immature.” But everyone seemed to agree there’s a need for ESL.

What’s the right messaging to EDA vendors?

The most memorable response here came from Philippe Magarshak of STMicroelectronics, who noted that EDA vendors respond to customer demands, some of which are not well thought out. “Maybe they do the wrong thing, having listened to users,” he said. In EDA, the customer is not always right.

Is the IP business model a product or a service?

The basic answer to this question is “yes.”

What’s the best part of your job – people or technology?

Turns out engineering managers are people-oriented after all. All but one answered “people.” Said Intel’s Rani Borkar: “There is no technology if there are no people to create it.”

Management Day was a fairly small and intimate event, held apart from the hustle and bustle of the DAC show floor. The stated goal was to “provide managers with timely information to help them make decisions where business and technology intersect.” So far as I can tell from the concluding session, and the reception that followed, the goal was met.

Richard Goering


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