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Guest Blog: The RF Challenge In Portable Designs

Comments(0)Filed under: Industry Insights, low power, Mixed-Signal, RF Integration, advanced node


The need for RF integration in consumer electronics presents some tough challenges, says veteran electronics industry editor John Donovan. He notes several emerging approaches that might help ease the challenge.

In simpler times most designs were digital. Add a few converters to handle I/O and you could ship the product. Consumer electronics—and cell phones in particular—changed all that. Now there are few consumer designs that don’t involve a large analog/mixed-signal component as well as multiple RF chains. Adding a few ADCs and DACs to the signal path isn’t enough; the three worlds are now heavily intertwined.

Digital and analog designs start with some basic differences. Digital designs tend to focus on the time domain, whereas analog designs are more concerned with the frequency domain. Digital designers worry about time delays; analog designers worry about the accuracy of their components, which they can’t change by editing a few lines of code. For RF designers there are no simple components; every resistor has stray capacitance and inductance, and every trace is an antenna. Parasitic extraction hits a whole new level of complexity in RF designs. RF integration is the single biggest challenge for SoC designers and a major headache at the board level, too.

Designing the RF front end for a cell phone involves some serious tradeoffs. The power amplifier (PA) is second only to the display as an energy hog in handsets. Modern handset receivers typically have a sensitivity in the range of -106 dBm. They also need to be able reject a 60 dB out-of-band signal without flattening the front end. The obvious solution is to crank up the power to the front end, since bandwidth and power are directly related—a tough tradeoff in a portable device.

In handsets you’ll also need to provide multiple RF chains that operate on different frequency bands for cellular, Bluetooth, Wi-Fi, UMTS, Mobile WiMAX, GPS and more. Oh, and you want DTV, DAB and FM with that, too? Just finding room on a tiny PC board for a combination of these protocols, each with different antennas operating at different frequencies—or MIMO antennas with multiple data streams—is problematic enough. Keeping them from interacting or radiating spurious signals back into the analog sections of the board is a serious headache. Integrating RF components onto silicon along side analog mixers, filters and LNAs is trickier still.

One way to ease the pain of RF integration is to go digital as quickly as possible. So-called “digital RF” doesn’t really replace a UHF sine wave with a string of bits, but it comes close. On the receive side, direct-conversion receivers combine direct RF sampling with discrete-time signal processing. The RF signal is sampled at the Nyquist rate, converted into packets, filtered, down-converted and fed to the baseband processor. The transmit PA, in one configuration, is a series of digital NMOS switches that feed a matching network. On-chip capacitors smooth the square waves into an RF sine wave that is then fed to the antenna. This approach can cut PA power consumption in half.

The tools to enable designers to simulate and verify an RF/mixed-signal design have only recently started to appear. Traditionally analog designers have used Spice models while their digital colleagues used VHDL or Verilog. Rationalizing the results was at best time consuming. Now we’re starting to see SystemC models that include concurrency, bit accuracy, timing and hierarchy, enabling designers working at the architectural level to do hardware/software co-design, synthesizing and verifying a design down to the silicon. We’re still not to the point where you can go smoothly from algorithmic exploration to netlists, but we’re getting there.

Someday soon analog and RF will no longer be the exclusive turf of grumpy greybeards in corner cubes. They’ll be just two more tools in every designer’s toolkit.

John Donovan

John Donovan is the editor of Low-Power Design (www.low-powerdesign.com), a new on-line publication. He was previously Editor-in-Chief of Portable Design, managing editor of EDN Asia and PR Director at Cypress Semiconductor. He has spent 25 years covering the electronics industry, focusing on semiconductor and wireless technologies. He can be reached at john@low-powerdesign.com.


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