Andrew B. Kahng is general chair of the 46th Design Automation Conference (DAC) set for July 26-31 in San Francisco. He is also a professor of Computer Science and Engineering (CSE) and Electrical and Computer Engineering (ECE) at the University of California at San Diego. In this Q&A interview, he describes what’s new and notable at DAC 2009 and discusses his expectations in light of today’s economic climate.
Q: We’re in an economic downturn that has severely impacted EDA vendors and their customers. What’s the impact on DAC this year?
A: We see impacts in the exhibition, since that is a reflection of the EDA and design industries. Travel budgets are impacted, so we’re trying to help attendees stretch their travel dollars. On the positive side, the DAC community has really come together to support DAC as the once-a-year meeting place for the industry. Paper submissions were noticeably up this year, especially in the areas of system-level design, low-power design, manufacturability issues, and high-level synthesis. San Francisco is a favorite destination, and the hotel prices are the lowest in years. Also, many workshops and industry groups are meeting alongside of DAC to offer synergies with respect to travel costs.
Q: What’s new and exciting about DAC this year?
A: First, the User Track – by, for, and selected by the users of EDA tools. This is complemented by other timely, design-focused events such as the Virtual Platform workshop and the SoC development-centric Management Day program. Second, the IC Design Central Partner Pavilion, a new area of the exhibit floor that hosts “IC Design Central” –– a cluster of exhibitors from across the semiconductor and electronics design supply chain. Third, the exhibitor forum has expanded due to strong demand. And we’re expecting a large contingent of bloggers and attendees using new media channels.
Q: The User Track is new in 2009. How is it structured, and what’s the basic idea?
A: We’re very happy with how the User Track has come together. Leon Stok of IBM and Soha Hassoun of Tufts University led the creation of this new part of DAC. The core idea is to serve the part of the design community that drives EDA tools. Until this year, the users of EDA tools did not have a dedicated forum at DAC. The User Track addresses this gap – and it really is by, for and chosen by the users of design tools. The 20 committee members represent a who’s-who of design teams and leading-edge methodology.
The User Track this year features more than 80 technical papers and posters presented by designers from around the world who will share their experiences creating today’s most complex chips. Its scope covers the latest innovations in tool use and design methodologies across the entire design process, from system design exploration and embedded software synthesis in the front end, to constraint generation and physical verification in the back end.
Q: What’s especially notable in this year’s keynote presentations and panels?
A: First, we have the Monday afternoon CEO panel with Aart de Geus of Synopsys, Wally Rhines of Mentor, and Lip-Bu Tan of Cadence. I cannot think of a subject more important to the EDA industry than what the CEOs of our three largest companies have to say about the future of EDA business and technology. With new leadership at Cadence, and with all the challenges we face, I believe this is a very timely return of the “CEO panel” to DAC.
On Tuesday and Wednesday, we have two of the most exciting and cutting-edge technology companies – TSMC and NVidia. The speakers – Fu-Chieh Hsu and Bill Dally – have done it all; technology innovation, technology leadership, and business leadership. Thursday afternoon brings a plenary panel on “Green” design and EDA moderated by Wally Rhines of Mentor Graphics. This is the first time that DAC has put together a lineup of keynote and plenary content Monday through Thursday – all available to anyone with an exhibits or conference badge.
Q: How many exhibitors do you expect? How does this compare to previous years?
A: We expect approximately 200 exhibitors, which is very similar to last year’s number. We are very glad that the four largest EDA vendors are all back on the floor, and we’re very excited about the increased presence of exhibitors from across the entire design chain of suppliers. We also have more than 25 new exhibitors this year.
Q: What does the “Exhibits” pass buy?
A: This year, exhibit-only registration gives access to all four days of the exhibition, the keynote sessions, all DAC pavilion and exhibitor forum sessions, plus the new IC Design Central Partner Pavilion.
Now that it’s past June 29, passes to the DAC exhibit floor are available for $95 prior to the conference. I should note that attendees can also get free access to the exhibit floor from exhibitors who are providing complimentary passes to their customers. Attendees need to contact their vendors to receive a complimentary exhibit-only registration code to be used during online registration at the DAC Web site.
Q: What do you expect in terms of attendance, and how does that compare to previous years?
A: We’re looking to maintain the level of 3,000-3,500 exhibitor participants, and to have as strong a showing as possible given the economy and budget constraints. There are still nearly four weeks until the conference, and typically it is during these last few weeks that the majority of DAC attendees wake up and register and find their hotel rooms.
Q: What technology themes do you think will be “hot” this year, either on the exhibit floor or in the conference program?
A: Obviously, the tool user perspective will be hot – that means details of design and chip development challenges, and practical solutions. For both vendors and researchers, system-level design, co-design and verification are hot. Physical and chip implementation issues – power management, manufacturability, reliability and integrity, and design closure – are still dominant user issues. Multicore SoC is another obvious topic on the minds of both EDA providers, algorithm researchers, and chip implementers. And in the technical conference we’re starting to see more of a critical mass of activity centered around beyond-CMOS and “nano” – including new memory and interconnect technologies.
Q: With so much information on line these days, why is it still important to attend DAC in person?
A: One answer is that quite a bit of DAC content – whether keynotes, special sessions, or even the conference papers – does not go online right away, or in some cases, ever. But more importantly, DAC is the opportunity for all of us in the EDA industry and the IC design ecosystem to come together once a year. It is the natural location for meaningful dialogue on the latest ideas and the key future directions across the industry. DAC is where the dialogue takes place. I believe that this year it’s even more important than ever that the community meet face-to-face to keep networking, learning, and moving forward.
Further information about the DAC program and registration is available at the DAC web site.