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Alberto Sangiovanni-Vincentelli Q&A: From IC Design To ‘Intelligent Buildings’

Comments(0)Filed under: Industry Insights, ASIC, FPGA, ESL, C-toSilicon Complier, ASSP, IC Design, GSRC


Alberto Sangiovanni-Vincentelli is a pioneer of the EDA industry, a professor of electrical engineering and computer science at the University of California at Berkeley, and a member of the Cadence Board of Directors. In this interview he talks about his latest work with energy-efficient buildings, which leverages some of the concepts used in IC design. He also shares his perspectives on system-level design.

Q: You’ve been working on the frontiers of system-level design for many years. What are you most excited about now?

A: I’m most excited about energy – about design methodologies and tools for energy efficiency. In particular, I’m excited about intelligent buildings.

Q: What goes into an intelligent building from the standpoint of energy savings?

A: A simple example is control of HVAC [heating, ventilation and air conditioning], which today is pretty lame. Large commercial buildings such as hotels and office buildings are consuming enormous amounts of energy. Approximately 40 percent of all energy consumed in the U.S. is in buildings.

Q: What are some of the ways we can make buildings more efficient?

A: In a hotel room, when you set the temperature, the air-conditioning system switches on and off all the time. This condition may be a pointer to energy inefficiency. Maybe the neighbor in the next room wants a different temperature than you, but since the rooms are adjacent, there is a continuous flow of air across a door that tends to even the temperature out. The air-conditioning systems in both rooms are fighting against each other, yielding a very inefficient situation.

There are better ways of doing this – for example, taking averages, and considering set points as recommendations from the user rather than God-given. You can play a little with the set points and make them more consistent so that the two air-conditioning systems do not fight continuously against each other.

To improve energy efficiency, you can be much cleverer about air flow. Also, heating and cooling depends very much on the number of people in the room. If you have a way of counting the number of people in the room, you can set your heating and air conditioning in a much better way than we do today. Another thing that comes to mind is the interaction between lighting and heating. If you can control lighting and heating together, that would be fantastic.

To optimize energy consumption, you should change completely the way you design a building. According to the orientation, and exposure to sun and wind, a building uses more or less energy. One should also take into consideration that energy can be generated inside a building.

We believe we can reduce [building] energy use by 80 percent. This is a goal that we can reach within a few years.

Q: What are the opportunities for IC designers and tool developers?

A: There is a terrific opportunity to instrument buildings for low energy consumption with intelligent closed-loop controllers that exploit wireless sensors and sophisticated actuators. And we need tools to select components, protocols, topologies and control algorithms to optimize energy consumption. There are some companies providing tools for designing control algorithms and deploying them into HVAC systems, but the situation is far from satisfactory.

I was doing this [building] work under GSRC [Gigascale Systems Research Center] a few years ago in collaboration with United Technologies, and people would say, “this guy is crazy, why does this have anything to do with the IC industry?” But Intel and TI have taken very interesting positions since then. Intel has been moving big time into the embedded systems arena, and they want to participate in embedded systems for low energy consumption. TI thinks it’s a place they can sell tons of chips. If, indeed, we start counting the number of rooms in buildings and consider the need for electronics to make buildings intelligent, it is easy to see that we need a huge number of ICs.

Q: What kinds of chips will go into intelligent buildings?

A: Wireless sensors are obvious ones. But you will also need intelligent controllers and actuators. You will need an interconnect infrastructure. I think you could integrate some of the IT functionality in a building with control functionality, as well as security subsystems.

My own view is that ASSPs are probably the way to go. FPGAs -- maybe, but they have higher costs. But more than FPGAs or ASICs, the big effort is going to be in sensors, actuators, power devices and software. Most control is going to be done by software.

Q: What are the software development challenges?

A: The difficulty with big buildings is scale. They are very large, and you need to control entire buildings. But this is just the beginning. Now imagine you have a number of buildings you can optimize together. Then you could think about common infrastructures and services such as providing common chill water and heating systems.

In buildings, there is a large effort in terms of safety, because you don’t want to have any accidents, and you want to have continuous availability of the system. You will have to think about fault tolerant architectures.

Q: How is intelligent building design related to EDA? Can EDA algorithms and methodologies help?

A: At the physical system level, it’s a mixed-signal problem. You have analog and IT aspects, and you have to mix and match differential equations with discrete logic. And that is what we’re facing in chips. You have to find appropriate abstractions for modeling, otherwise the sheer complexity of buildings will make analysis and optimization simply impossible. Thus we are working to find a modeling strategy [for buildings] that allows multi-level models to be connected together. That is something we’ve been doing in the electronics domain as well.

Q: You’ve been advocating platform-based design [PBD] for many years, and it’s been applied to SoC design and automotive design. Does it also apply to building design?

A: Oh, yes. Indeed we are working on research projects that aim at introducing this methodology into the design of energy efficient buildings. As is common in the PBD methodology, we need to decompose the problem into levels of abstraction and provide logical connectivity among the different levels. The meet-in-the-middle paradigm of PBD requires one to select a library of available components, to characterize their performance and energy utilization, and to provide an algebra to compute these quantities in a compositional way in a bottom-up phase. The requirements flow in the opposite direction -- from specification towards implementation.

Q: Turning to EDA, there’s been a lot of talk about ESL in the past few years. Is ESL as we’ve defined it a big enough vision for system-level design?

A: I don’t think so. The platform-based design paradigm, with its way of considering the architecture and functionality of the design, has not taken place in our [EDA] domain as yet. SystemVerilog – that’s what people call a system level design tool. It is not exactly what I would consider system-level design abstraction, though.

Q: From an EDA perspective, what’s practical in the short term with respect to system-level design?

A: In the short term, I think the only path to it – without trying to be revolutionary – is to extend upwards from where we are today. I believe SoCs are the opportunity now. You want to have an environment where you can plug and play different IP blocks, quickly verify your design, and make sure you have a path to manufacturing. Lo and behold, this process can be cast into the principles of platform-based design. There is a library of IP components -- which implicitly defines a platform -- and rules according to which you assemble a solution, rules that use the costs associated with that solution.

Q: What’s possible in the longer run for system-level design?

A: If you look at the recent tragic Air France accident, where some believe its causes are to be found in the catastrophic failure of an electronic subsystem, it points to verification before implementation as being a key technology to prevent such accidents from occuring again. There there will be a increasing push towards virtual analysis, because it is too costly to design an [Airbus] 787 and use it as a debugging environment. Virtualization of design will be a major push, whether in the transportation industry, defense industry, or building industry.

To enter into this new era of design you will need a tremendous amount of work in modeling. A key difficulty in system-level design is modeling.

Q: How can the EDA industry help with the embedded software challenge? Are there tools or methodologies that can help?

A: Absolutely. Formal verification of software could be one big help, especially in a safety-driven situation, albeit you could argue that formal verification is not really an EDA invention – the first example of its use was for protocol design at AT&T many years ago.

But when you talk about software design, it is really too late to identify system-level design errors. Think of software as the result of a process that begins with functionality capture and then proceeds towards implementation by selecting a computing platform and realizing the functionality as software running on that computing platform. This process is the essence of model-driven design, which is gaining increasing attention in the design community. In model-based design, software could be automatically “synthesized” from high level specifications.

In automotive design, model-driven design is clearly the way to go. You can design a mathematical model in Simulink and map it into software using Real-Time Workshop. Hence, software becomes an implementation choice. You don’t really need to verify the software if you trust the RTW code generator; you need to verify what comes before software -- that is, you must take a a functional point of view.

Q: Finally, where do you see Cadence’s opportunities in this emerging era of system-level design?

A: C-to-Silicon Compiler is one step towards that vision. The idea was one of mapping functionality onto a piece of architecture, and then evaluating it. In my view there is a great opportunity for C-to-Silicon Compiler – it is a leg up.

In mixed-signal design, we are trying to make analog reusable, in which case analog components can be seen as a component of a platform. I think it’s a great opportunity for Cadence. We are coming from where we’ve been strong in the past and moving up.

Richard Goering


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