Veteran IC designer Steve Padnos notes that low-power design starts with a clear understanding of objectives – a process that is easy to overlook. He provides suggestions that can help designers meet this challenge.
Over the last several years, power has moved from an afterthought to a major concern in chip design. Power must now be considered a primary factor along with performance, cost and schedule. To take advantage of opportunities for power reduction, designers must think about power at all phases of a chip’s lifecycle. The entire process starts with having a clear understanding of the objectives. While this may sound obvious, in my experience it is often overlooked or oversimplified.
Designers have come up with a long list of techniques to reduce power. These techniques are well documented in a number of places. The EDA industry has responded with a number of tools, or enhancements to existing tools, to support power analysis and optimization. Before deciding which low-power techniques are appropriate for a particular design, it is necessary to know how they will impact the power consumption of the design.
The first part of the problem is realizing that specifying power is not easy. Specifying a target die size is simple. Timing is a little more complex. You have different timing modes and you need to worry about setup and hold in each. But power is more complicated still. Not only will there be different power consumption in each of the timing modes, but there also may be multiple power modes. Static timing analysis can eliminate the need for dynamic timing simulations, but for power, identifying good vectors is essential and usually not easy.
Identifying the different physical modes is still not sufficient. There are many reasons to reduce power, including fitting into a less expensive package, eliminating the need for a heat sink or fan, conforming to form factor limitations, and maximizing battery life. For some of these objectives the concern is power, but for others the real concern is energy (power integrated over time). What is needed is a higher-level model of chip (or even the system) power that will enable designers to find the power reduction techniques that will have the highest return on investment for their particular application.
Almost all chips today have different operating profiles. This could be as simple as normal operation and test. For example, a smartphone will have power profiles for when it is idle -- profiles for when you are playing an MP3, for when you are talking on the phone, or for when the chip is being tested during manufacturing. Each of these profiles will in turn be composed of multiple physical modes in the chip. Blocks will be powered on or off, clock frequencies may be adjusted, and voltages will be set.
When you talk on the phone it is probably going in and out of transmit, receive and idle modes. To understand the power in this “talking” profile you need to understand the power in each of those modes, the time in each mode, and the transitions between modes.
The profiles of interest need to be defined as part of the specification process. There needs to be a power requirement for each profile. As an example consider a scan profile. The profile is composed of two modes: scan and capture. The power dissipation will be very different during scan than it will be during capture. While you may not care about battery life during test you do care about IR drop.
Most power reduction techniques involve tradeoffs with area, performance, scheduling or even dynamic power versus leakage. A simple spreadsheet will provide a lot of mileage. The spreadsheet can cover the different profiles, the power consumption of all the blocks or subsystems in the design, and the power consumption of each in the different modes.
It is important to look at power consumption weighted by time. A block may have high peak power, but if it is only active for a very small amount of time the total energy may not be significant. Because we tend to think more in terms of power than energy, I have seen unintuitive results. The spreadsheet may not be able to factor in schedule, performance or cost, but it will provide feedback on the potential power savings.
Engineering has been described as the science of compromise. Failure to invest in good requirements makes it impossible to make good tradeoffs.
Steve Padnos has spent over 20 years working on chip design, EDA and IP. Over the years he has been involved in all phases of the design from architecture through tapeout and has worked on a wide variety of designs. He can be reached at firstname.lastname@example.org.