A recent decision by TSMC to require model-based design for manufacturability (DFM) checks at 45/40 nm may push DFM into more widespread use. It’s coming too late for the several dozen DFM startups that were around a few years ago, but it could have a significant impact on IC design flows going forward.
At 45/40 nm, TSMC mandates that users run a lithography process check (LPC) and virtual chemical/mechanical simulation (VCMP). The VCMP requirement is waived for blocks less than 1 mm2. LPC and VCMP were recommended, rather than mandatory, at 65 nm and above. For rule-based DFM, layout parameter extraction (LPE) is a new requirement at 45/40 nm.
Rule-based recommendations and mandates have been around for years, but model-based DFM is relatively new – and it’s been an area of intense focus for established EDA providers and startups alike. Without foundry requirements, however, adoption has not been as fast as some might have expected. Model-based checks typically include LPC, CMP, and critical area analysis (CAA).
Why the change from recommended to mandatory for LPC and VCMP? Tom Quan, deputy director of design methodology and service marketing at TSMC, said that TSMC has been running its own model-based checks at 65 nm and above, and working with customers to fix any problems that arise. “We think that might not be doable [at 45/40 nm] given the complexity of some of the designs that are coming in, and we want to make sure the customer will do some level of model-based checking beforehand,” he said. “Rules are getting so complex that there is no way the customer can use a complete rule-based solution.”
The growing complexity of unrestricted layout patterns has also led to the requirement for LPC and VCMP checks, Quan said. But CAA is still recommended rather than required at 45/40 nm, he said, because “systematic and random defects at 40 and 45 nm are under good control.”
Unlike TSMC, Chartered does not mandate model-based DFM checks at 45 nm. “However,” said Walter Ng, vice president of design enablement alliances at Chartered, “we have noticed that more customers designing at 45 nm and below are more proactive in taking up DFM.” Chartered recommends model-based checks and has used them with some customers and with library and IP partners.
Manoj Chacko, director of product marketing for DFM and extraction at Cadence, said he’s noticed an increase in customer inquiries about model-based DFM beginning early this year. “40 nm customers are asking what the tools offer and are saying they need model-based DFM,” he noted.
Quan noted that mandatory checks today may not always be mandatory. Over time, some could go back into the “recommended” column as more experience is gained with the process. Further, restricted design rules (RDRs) may moderate the need for model-based DFM in the future. TSMC doesn’t have RDRs at 45 nm, but expects to have some at 32 and 28 nm. “If you have a lot of patterns you don’t need to worry about, it could mean that the model-based approach doesn’t have to become more complex,” he said.
TSMC customers have two options for meeting the model-based DFM mandates. First, they can use commercial tools such as the Cadence Litho Physical Analyzer (LPA), Cadence Litho Electrical Analyzer (LEA), and Cadence CMP Predictor (CCP). Secondly, they can use TSMC’s on-line DFM service. Quan said the service can be cost-effective for small customers, but it requires customers to wait a few days while TSMC runs the checks. Larger customers who already have EDA tool licenses will probably use their own tools, he said.
One way or another, it appears that model-based DFM is finally moving from the “talking” stage to becoming a necessary part of the IC design flow.